A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

2002 ◽  
Vol 23 (5) ◽  
pp. 237-239 ◽  
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Jau-Yi Wu ◽  
Hwei-Heng Wang ◽  
Po-Wen Sze ◽  
Yeong-Her Wang ◽  
Mau-Phon Houng
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Hou-Kuei Huang ◽  
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...  

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Yeong-Her Wang

1998 ◽  
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Chien-Jung Huang ◽  
Yeong-Her Wang ◽  
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Vacuum ◽  
2020 ◽  
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Yi-Shiang Chen ◽  
Ching-Yi Kao ◽  
Kuan-Wei Lee ◽  
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1999 ◽  
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Hwei‐Heng Wang ◽  
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Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.


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