Positive flatband voltage shift in MOS capacitors on n-type GaN

2002 ◽  
Vol 23 (2) ◽  
pp. 79-81 ◽  
Author(s):  
K. Matocha ◽  
T.P. Chow ◽  
R.J. Gutmann
Keyword(s):  
Mos Capacitors ◽  
Voltage Shift ◽  
Flatband Voltage

Promising Gate Stacks with Ru & RuO2 Gate Electrodes and Y-silicate Dielectrics

2001 ◽  
Vol 670 ◽  
Author(s):  
Huicai Zhong ◽  
Greg Heuss ◽  
You-Seok Suh ◽  
Shin-Nam Hong ◽  
Veena Misra ◽  
...  
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Oxide Thickness ◽  
Grain Structure ◽  
Mos Capacitors ◽  
Thickness Change ◽  
Voltage Shift ◽  
Gate Electrodes ◽  
High Temperature Anneal ◽  
Flatband Voltage

ABSTRACTIn this work, we studied the electrical and thermal stability of Ru and RuO2 electrode on Y-silicate dielectrics in contrast to ZrO2 and Al2O3 dielectrics. Very low resistivity Ru and rutile stoichiometric RuO2 films, deposited via reactive sputtering, were evaluated as gate electrodes on ultrathin Y-silicate, ZrO2 and Al2O3 films for Si-MOS devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures up to 800°C in N2 and subsequently forming gas anneal. XRD and XPS were measured to study grain structure and interface reactions. The morphology of the films was tested by atomic force microscopy (AFM). Electrical properties were evaluated via MOS capacitors. The role of oxygen inside dielectrics was studied by comparing equivalent oxide thickness change as a function of annealing temperature for capacitors with Y-silicate, ZrO2and Al2O3 dielectrics. Good stability of Ru and RuO2 gate electrodes on all dielectrics studied was found. Flatband voltage and gate current as a function of annealing temperature was also studied. It was found that capacitors with Y-silicate after high-temperature anneal had less positive flatband voltage shift than ZrO2 and Al2O3. For capacitors with Ru gate electrode, the significant flatband voltage shift after high temperature anneal could be partially removed by a forming gas anneal.

scholarly journals Positive flatband voltage shift in phosphorus doped SiO2/N-type 4H-SiC MOS capacitors under high field electron injection

2019 ◽  
Vol 52 (50) ◽  
pp. 505102
Author(s):  
M I Idris ◽  
M H Weng ◽  
A Peters ◽  
R J Siddall ◽  
N J Townsend ◽  
...  
Keyword(s):  
High Field ◽  
Electron Injection ◽  
Mos Capacitors ◽  
Voltage Shift ◽  
Field Electron ◽  
Flatband Voltage ◽  
Phosphorus Doped

Flatband Voltage Shift Depending on SiO2/SiC Interface Charges in 4H-SiC MOS Capacitors with AlON/SiO2 Stacked Gate Dielectrics

2016 ◽  
Vol 858 ◽  
pp. 681-684 ◽  
Author(s):  
Takuji Hosoi ◽  
Shuji Azumo ◽  
Kenji Yamamoto ◽  
Masatoshi Aketa ◽  
Yusaku Kashiwagi ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Aluminum Oxynitride ◽  
Equivalent Thickness ◽  
Mos Capacitors ◽  
Voltage Shift ◽  
Interface Charges ◽  
Linear Fit ◽  
Flatband Voltage

The mechanism of flatband voltage shift in SiC metal-oxide-semiconductor (MOS) capacitors with stacked gate dielectrics consisting of aluminum oxynitride (AlON) layers and SiO2 underlayers was investigated by varying the AlON and SiO2 thicknesses. The flatband voltages of the fabricated capacitors with fixed SiO2 underlayer thicknesses were almost independent of the AlON thickness, indicating the negligible charges in AlON layer. On the other hand, when varying SiO2 underlayer thickness, the flatband voltage decreased with an increase in capacitance equivalent thickness (CET), and the slope of their linear fit was comparable to that for SiC MOS capacitors without AlON layer. These observations can be well explained by assuming interface charges at AlON/SiO2 interface with an amount comparable, but a polarity opposite to, those at SiO2/SiC interface.

Experimental Identification of Extra Type of Charges at SiO2/SiC Interface in 4H-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 519-522 ◽  
Author(s):  
Harsh Naik ◽  
Z. Li ◽  
T. Paul Chow
Keyword(s):  
High Temperature ◽  
Temperature Dependence ◽  
Processing Conditions ◽  
Mos Capacitors ◽  
Voltage Shift ◽  
Experimental Identification ◽  
Uv Illumination ◽  
Fixed Charges ◽  
Flatband Voltage

High temperature C-V characterization with and without UV illumination has been performed on n-type 4H-SiC MOS capacitors fabricated using different processing conditions to extract various types of interfacial charges. An anomalous positive flatband voltage shift with temperature has been observed in most of the SiC MOS capacitors measured. We have experimentally identified an extra type of fixed charges at the 4H-SiC/SiO2 interface from the temperature dependence of the flatband voltage, particularly under UV illumination.

Analysis of 3-Dimensional 4H-SiC MOS Capacitors Grown by Atomic Layer Deposition of Al2O3

2018 ◽  
Vol 924 ◽  
pp. 490-493 ◽  
Author(s):  
Muhammad I. Idris ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
3 Dimensional ◽  
Layer Deposition ◽  
Show Evidence ◽  
Flatband Voltage

3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

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