A method for consistent fault coverage reporting

1993 ◽  
Vol 10 (3) ◽  
pp. 68-79 ◽  
Author(s):  
W.H. Debany ◽  
K.A. Kwiat ◽  
S.A. Al-Arian
Keyword(s):  
Fault Coverage

A new BIST scheme with encoding logic to achieve complete fault coverage

2015 ◽  
Author(s):  
Ling Zhang ◽  
Junjin Mei ◽  
Guan-zhong Wang ◽  
Tonghan Li
Keyword(s):  
Fault Coverage

scholarly journals Fault Coverage-Aware Metrics for Evaluating the Reliability Factor of Solar Tracking Systems

Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 1074
Author(s):  
Raul Rotar ◽  
Sorin Liviu Jurj ◽  
Flavius Opritoiu ◽  
Mircea Vladutiu
Keyword(s):  
High Performance ◽  
Computation Time ◽  
Fault Coverage ◽  
Programming Environment ◽  
Tracking Systems ◽  
Circuit Testing ◽  
Reliability Factor ◽  
Solar Tracking ◽  
Mathcad Software ◽  
Python Programming

This paper presents a mathematical approach for determining the reliability of solar tracking systems based on three fault coverage-aware metrics which use system error data from hardware, software as well as in-circuit testing (ICT) techniques, to calculate a solar test factor (STF). Using Euler’s named constant, the solar reliability factor (SRF) is computed to define the robustness and availability of modern, high-performance solar tracking systems. The experimental cases which were run in the Mathcad software suite and the Python programming environment show that the fault coverage-aware metrics greatly change the test and reliability factor curve of solar tracking systems, achieving significantly reduced calculation steps and computation time.

scholarly journals Construction and application of march tests for pattern sensitive memory faults detection

Informatics ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 25-42
Author(s):  
V. N. Yarmolik ◽  
V. A. Levantsevich ◽  
D. V. Demenkovets ◽  
I. Mrozek
Keyword(s):  
Fault Detection ◽  
Multiple Testing ◽  
High Efficiency ◽  
Fault Coverage ◽  
Memory Cells ◽  
March Test ◽  
Storage Devices ◽  
Coupon Collector ◽  
March Tests ◽  
Analytical Expressions

The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms of march test elements the conditions for activation and fault detection of PNPSFk of storage devices. Examples of march tests with maximum fault coverage, as well as march tests with a minimum time complexity equal to 18N are given. The efficiency of a single application of tests such as MATS ++, March C− and March PS is investigated for different number of k ≤ 9 memory cells involved in PNPSFk fault. The applicability of multiple testing with variable address sequences is substantiated, when the use of random sequences of addresses is proposed. Analytical expressions are given for the fault coverage of complex PNPSFk faults depending on the multiplicity of the test. In addition, the estimates of the mean value of the multiplicity of the MATS++, March C− and March PS tests, obtained on the basis of a mathematical model describing the problem of the coupon collector, and ensuring the detection of all k2k PNPSFk faults are given. The validity of analytical estimates is experimentally shown and the high efficiency of PNPSFk fault detection is confirmed by tests of the March PS type.

scholarly journals Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Fault Coverage ◽  
Test Vector ◽  
Single Event Upset ◽  
Fault Models ◽  
Test Program ◽  
Global Test ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction ◽  
Selection Of

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

Sign in / Sign up

Export Citation Format

Share Document