Cache memories

2000 ◽  
Vol 19 (2) ◽  
pp. 24-29 ◽  
Author(s):  
R. Stacpoole ◽  
T. Jamil
Keyword(s):  
Cache Memories

scholarly journals Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

2018 ◽  
Vol 37 (7) ◽  
pp. 1345-1357 ◽  
Author(s):  
Daniele Rossi ◽  
Vasileios Tenentes ◽  
Sudhakar M. Reddy ◽  
Bashir M. Al-Hashimi ◽  
Andrew Brown
Keyword(s):  
Cache Memories

scholarly journals Software Time Reliability in the Presence of Cache Memories

2017 ◽  
pp. 233-249 ◽  
Author(s):  
Suzana Milutinovic ◽  
Jaume Abella ◽  
Irune Agirre ◽  
Mikel Azkarate-Askasua ◽  
Enrico Mezzetti ◽  
...  
Keyword(s):  
Cache Memories

scholarly journals End-to-end automated cache-timing attack driven by Machine Learning

10.29007/nwj8 ◽  
2019 ◽  
Author(s):  
Sebastien Carré ◽  
Victor Dyseryn ◽  
Adrien Facon ◽  
Sylvain Guilley ◽  
Thomas Perianin
Keyword(s):  
Neural Network ◽  
Language Processing ◽  
Relevant Information ◽  
Security Threats ◽  
Cache Memories ◽  
Function Calls ◽  
Timing Data ◽  
Timing Attack ◽  
End To End ◽  
Timing Attacks

Cache timing attacks are serious security threats that exploit cache memories to steal secret information.We believe that the identification of a sequence of operations from a set of cache-timing data measurements is not a trivial step when building an attack. We present a recurrent neural network model able to automatically retrieve a sequence of function calls from cache-timings. Inspired from natural language processing, our model is able to learn on partially labelled data. We use the model to unfold an end-to-end automated attack on OpenSSL ECDSA on the secp256k1 curve. Contrary to most research, we did not need human processing of the traces to retrieve relevant information.

scholarly journals A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 709
Author(s):  
Abhishek Das ◽  
Nur A. Touba
Keyword(s):  
Optimization Technique ◽  
Error Correcting Code ◽  
Latin Square ◽  
Error Correcting Codes ◽  
Trade Off ◽  
Cache Memories ◽  
Hamming Codes ◽  
Single Error ◽  
Memory Overhead ◽  
On Chip

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.

scholarly journals Applying March Tests to K-Way Set-Associative Cache Memories

2008 ◽  
Author(s):  
Simone Alpe ◽  
Stefano Di Carlo ◽  
Paolo Prinetto ◽  
Alessandro Savino
Keyword(s):  
Cache Memories ◽  
March Tests
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