scholarly journals On automatic-verification pattern generation for SoC with port-order fault model

2002 ◽  
Vol 21 (4) ◽  
pp. 466-479 ◽  
Author(s):  
Chun-Yao Wang ◽  
Shing-Wu Tung ◽  
Jing-Yang Jou
Keyword(s):  
Fault Model ◽  
Pattern Generation ◽  
Automatic Verification

scholarly journals Test

2021 ◽  
pp. 381-391
Author(s):  
Peter Marwedel
Keyword(s):  
Physical System ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Fault Simulation ◽  
Fault Coverage ◽  
Fault Model ◽  
Pattern Generation ◽  
Signature Analysis ◽  
Fault Tolerant Systems ◽  
Random Patterns

AbstractUnfortunately, we cannot rely on designed and possibly already manufactured systems to operate as expected. These systems may have become defective during their use, or their function may have been compromised during the fabrication or their design. The purpose of testing is to verify whether or not an existing embedded/cyber-physical system can be operated as expected. In this chapter, we will present fundamental terms and techniques for testing. There will be a brief introduction to the aims of test pattern generation and their application. We will be introducing terms such as fault model, fault coverage, fault simulation, and fault injection. Also, we will be presenting techniques which improve testability, including the generation of pseudo-random patterns, and signature analysis. It would be beneficial to consider testability issues already during design. In case of fault-tolerant systems, resilience must be verified.

scholarly journals Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults

VLSI Design ◽  
1998 ◽  
Vol 7 (2) ◽  
pp. 163-176 ◽  
Author(s):  
Gerald Spiegel ◽  
Albrecht P. Stroele
Keyword(s):  
Structural Changes ◽  
Fault Modeling ◽  
Fault Coverage ◽  
Fault Model ◽  
Pattern Generation ◽  
Analysis Method ◽  
Bridging Faults ◽  
Probability Of Occurrence

Fault sets that accurately describe physical failures are required for efficient pattern generation and fault coverage evaluation. The fault model presented in this paper uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including bridging faults that connect more than two nets, break faults that break a net into more than two parts, and compound faults. The developed analysis method extracts the comprehensive set of realistic faults from the layout of CMOS ICs and for each fault computes the probability of occurrence. The results obtained by the tool REFLEX show that bridging faults connecting more than two nets account for a significant portion of all faults and cannot be neglected.

AlCu Pattern Generation on 3D StructuredWafer Using Multi Level Exposure Method on Electrodeposited Polymer Material

2003 ◽  
Vol 766 ◽  
Author(s):  
Vineet Sharma ◽  
Arief B. Suriadi ◽  
Frank Berauer ◽  
Laurie S. Mittelstadt
Keyword(s):  
Line Width ◽  
Metal Film ◽  
Focal Depth ◽  
Cost Effective ◽  
Pattern Generation ◽  
Promising Technique ◽  
Critical Dimensions ◽  
Exposure Method ◽  
Multi Level ◽  
3D Surfaces

AbstractNormal photolithography tools have focal depth limitations and are unable to meet the expectations of high resolution photolithography on highly topographic structures. This paper shows a cost effective and promising technique of combining two different approaches to achieve critical dimensions of traces on slope pattern continuity on highly topographic structures. Electrophoretically deposited photoresist is used on 3-D structured wafers. This photoresist coating technique is fairly known in the MEMS industries to achieve uniform and conformal photoresist films on 3D surfaces. Multi step exposures are used to expose electrophoretically deposited photoresist. AlCu (Cu-0.5%), 0.47-0.53 μm thick metal film is deposited on 3D structured silicon substrate to plate photoresist. By combining these two novel methods, metal (AlCu) traces of 75 μm line width and 150 μm pitch (from top flat to down the slope) have been demonstrated on isotropically etched 350 μm deep trenches with 5-10% line width loss.

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