A heuristic standard cell placement algorithm using constrained multistage graph model

1988 ◽  
Vol 7 (11) ◽  
pp. 1205-1214 ◽  
Author(s):  
Hwan Gue Cho ◽  
C.M. Kyung
Keyword(s):  
Graph Model ◽  
Standard Cell ◽  
Cell Placement ◽  
Placement Algorithm

scholarly journals Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Technologies ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 3
Author(s):  
Panagiotis Oikonomou ◽  
Antonios Dadaliaris ◽  
Kostas Kolomvatsos ◽  
Thanasis Loukopoulos ◽  
Athanasios Kakarountas ◽  
...  
Keyword(s):  
Target Function ◽  
Problem Formulation ◽  
Search Space ◽  
Standard Cell ◽  
Chip Area ◽  
Time Performance ◽  
Trade Offs ◽  
Cell Placement ◽  
Placement Algorithm ◽  
Algorithmic Approaches

In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

scholarly journals Standard Cell Placement Optimization Using Quadratic Placement Algorithm

OALib ◽  
2020 ◽  
Vol 07 (04) ◽  
pp. 1-7
Author(s):  
Suren Abazyan ◽  
Narek Mamikonyan ◽  
Vakhtang Janpoladov
Keyword(s):  
Standard Cell ◽  
Placement Optimization ◽  
Cell Placement ◽  
Placement Algorithm

scholarly journals IFDR: An Efficient Iterative Optimization Algorithm for Standard Cell Placement

2004 ◽  
Vol 27 (4) ◽  
pp. 189-195
Author(s):  
Feng Cheng ◽  
Junfa Mao
Keyword(s):  
Integrated Circuits ◽  
Optimization Algorithm ◽  
Electrical Circuit ◽  
Standard Cell ◽  
Placement Problem ◽  
Iterative Optimization ◽  
Automatic Placement ◽  
Cell Placement ◽  
Placement Algorithm ◽  
Iterative Optimization Algorithm

In the automatic placement of integrated circuits, the force directed relaxation (FDR) method [Goto, S. (1981). An efficient algorithm for the two-dimensional placement problem in electrical circuit layout.IEEE Trans. on Circuits and Systems,CAS-28(1), 12-18] is a good iterative optimization algorithm. In this article, an improved force directed relaxation (IFDR) method for standard cell placement is presented, which provides a more flexible and efficient cell location adjustment scheme and a more extensive searching scale for better iterative placement optimization than the FDR method. A new heuristic algorithm based on local optimization is combined with the IFDR method to improve the placement. Experiments on the Microelectronics Center of North Carolina (MCNC) standard cell benchmarks [http://www.cbl.ncsu.edu/pub/Benchmark_ dirs/Layout Synth92/] have been done, and the results show that total wire length is reduced up to 25% and by an average of 16% in comparison with that from the placement algorithm of TimberWolf7.0.

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