scholarly journals An integrated logical and physical design flow for deep submicron circuits

1999 ◽  
Vol 18 (9) ◽  
pp. 1305-1315 ◽  
Author(s):  
A.H. Salek ◽  
Jinan Lou ◽  
M. Pedram
Keyword(s):  
Deep Submicron ◽  
Physical Design ◽  
Design Flow ◽  
Deep Submicron Circuits

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Heechun Park ◽  
Bon Woong Ku ◽  
Kyungwook Chang ◽  
Da Eun Shim ◽  
Sung Kyu Lim
Keyword(s):  
State Of The Art ◽  
Physical Design ◽  
Design Flow ◽  
Design Tools ◽  
Mixed Design ◽  
Power Performance ◽  
3D Design ◽  
Qualitative And Quantitative ◽  
3D Ics ◽  
Power Delay Product

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

Physical Design Flow for 3D /CoWoS® Stacked IC s

2019 ◽  
pp. 81-114
Author(s):  
Yu‐Shiang Lin ◽  
Sandeep K. Goel ◽  
Jonathan Yuan ◽  
Tom Chen ◽  
Frank Lee
Keyword(s):  
Physical Design ◽  
Design Flow

A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding

2020 ◽  
Vol 39 (10) ◽  
pp. 2152-2165
Author(s):  
Huanyu Wang ◽  
Qihang Shi ◽  
Adib Nahiyan ◽  
Domenic Forte ◽  
Mark M. Tehranipoor
Keyword(s):  
Physical Design ◽  
Design Flow ◽  
Front Side ◽  
Probing Attacks

Power Supply Distribution and Other Wiring Issues For deep-submicron Ic's

1998 ◽  
Vol 514 ◽  
Author(s):  
W. T. Lynch ◽  
L. A. Arledge
Keyword(s):  
Density Function ◽  
Power Supply ◽  
Decision Process ◽  
Deep Submicron ◽  
Physical Design ◽  
Design And Technology ◽  
Gate Delay ◽  
Wire Length ◽  
Clock Period ◽  
Architecture Optimization

ABSTRACTAn Interconnect Architecture Optimization (IAO) methodology is proposed. The algorithm makes use of fundamental RLCLL2 relations for wiring delays, as well as predictive 3D interconnect density function histograms with y and x axes of wire length and inverse gate delay. The fundamental RLCLL2 relations determine “maximum” wire lengths as a function of wiring size within the wiring hierarchy; the 3D histogram establishes the pre-physical design allocations of wiring nets within the hierarchy. The decision process begins with the set-asides of wiring for power, clock, and vias, and ends with an optimized number of wiring levels and sizes. Some of the major conclusions of the preliminary analyses are: there are no significant problems with wiring at the lowest level as long as the local wire lengths are appropriately scaled; the MOSFET device may not be able to provide enough current to satisfy the capacitive fanout loads within the future allocations of clock period; and the global wires, despite significant improvements in performance, will continue to provide a design and technology challenge for larger chips and higher frequencies.

PHYSICAL DESIGN FOR AN ARM CHIP UNDER DEEP SUBMICRON TECHNOLOGY

2016 ◽  
Author(s):  
Ying-Jun Zeng ◽  
Zhi-Jing Zhang ◽  
Mao-Dong Wang ◽  
Wei Gao
Keyword(s):  
Deep Submicron ◽  
Physical Design

scholarly journals A quantum physical design flow using ILP and graph drawing

2013 ◽  
Vol 12 (10) ◽  
pp. 3239-3264 ◽  
Author(s):  
Maryam Yazdani ◽  
Morteza Saheb Zamani ◽  
Mehdi Sedighi
Keyword(s):  
Graph Drawing ◽  
Physical Design ◽  
Design Flow
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