Gate matrix partitioning

S. Huang; O. Wing

doi:10.1109/43.31533

Gate matrix partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.31533 ◽

1989 ◽

Vol 8 (7) ◽

pp. 756-767 ◽

Cited By ~ 10

Author(s):

S. Huang ◽

O. Wing

Keyword(s):

Gate Matrix ◽

Matrix Partitioning

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Gate matrix partitioning

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122478 ◽

2003 ◽

Author(s):

Shuo Huang ◽

O. Wing

Keyword(s):

Gate Matrix ◽

Matrix Partitioning

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GM-learn: an iterative learning algorithm for CMOS gate matrix layout

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1990.0037 ◽

1990 ◽

Vol 137 (4) ◽

pp. 301 ◽

Cited By ~ 1

Author(s):

Sao-Jie Chen ◽

Yu Hen Hu

Keyword(s):

Learning Algorithm ◽

Iterative Learning ◽

Gate Matrix

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Development of a design structure matrix partitioning method towards effective design collaboration

International Journal of Manufacturing Technology and Management ◽

10.1504/ijmtm.2012.048705 ◽

2012 ◽

Vol 25 (4) ◽

pp. 177 ◽

Cited By ~ 1

Author(s):

Zhixin Yang ◽

Jie Zhou ◽

Chao Deng ◽

Xin yu Shao

Keyword(s):

Design Structure Matrix ◽

Structure Matrix ◽

Design Collaboration ◽

Design Structure ◽

Matrix Partitioning ◽

Effective Design

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Matrix partitioning code family for spectral amplitude coding OCDMA

Photonic Network Communications ◽

10.1007/s11107-014-0439-1 ◽

2014 ◽

Vol 28 (1) ◽

pp. 102-111 ◽

Cited By ~ 3

Author(s):

Hassan Yousif Ahmed

Keyword(s):

Spectral Amplitude ◽

Spectral Amplitude Coding ◽

Matrix Partitioning

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Column-Based Matrix Partitioning for Parallel Matrix Multiplication on Heterogeneous Processors Based on Functional Performance Models

Euro-Par 2011: Parallel Processing Workshops - Lecture Notes in Computer Science ◽

10.1007/978-3-642-29737-3_50 ◽

2012 ◽

pp. 450-459 ◽

Cited By ~ 19

Author(s):

David Clarke ◽

Alexey Lastovetsky ◽

Vladimir Rychkov

Keyword(s):

Functional Performance ◽

Matrix Multiplication ◽

Performance Models ◽

Heterogeneous Processors ◽

Matrix Partitioning

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An improved min-net-cut approach for gate-matrix and metal-metal matrix circuit layout

10.1109/mwscas.1989.101914 ◽

2003 ◽

Cited By ~ 1

Author(s):

P. Gee ◽

I.N. Hajj ◽

S.M. Kang

Keyword(s):

Metal Matrix ◽

Circuit Layout ◽

Metal Metal ◽

Gate Matrix

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Obstruction set isolation for the gate matrix layout problem

Discrete Applied Mathematics ◽

10.1016/0166-218x(94)90021-3 ◽

1994 ◽

Vol 54 (2-3) ◽

pp. 169-213 ◽

Cited By ~ 30

Author(s):

Nancy G. Kinnersley ◽

Michael A. Langston

Keyword(s):

Layout Problem ◽

Gate Matrix

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A dense gate matrix layout method for MOS VLSI

IEEE Transactions on Electron Devices ◽

10.1109/t-ed.1980.20086 ◽

1980 ◽

Vol 27 (8) ◽

pp. 1671-1675 ◽

Cited By ~ 98

Author(s):

A.D. Lopez ◽

H.-F.S. Law

Keyword(s):

Gate Matrix

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Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach

Integration ◽

10.1016/0167-9260(92)90025-t ◽

1992 ◽

Vol 14 (2) ◽

pp. 173-195 ◽

Cited By ~ 4

Author(s):

A.G. Ferreira ◽

S.W. Song

Keyword(s):

Theoretic Approach ◽

Graph Theoretic ◽

Graph Theoretic Approach ◽

Gate Matrix

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An efficient hybrid heuristic for the gate matrix layout problem in VLSI design

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282686 ◽

2002 ◽

Author(s):

T. Bagchi ◽

S.K. Das

Keyword(s):

Vlsi Design ◽

Layout Problem ◽

Hybrid Heuristic ◽

Gate Matrix

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