A RISC processor for embedded applications within an ASIC

IEEE Micro ◽  
1991 ◽  
Vol 11 (5) ◽  
pp. 20-23
Author(s):  
C.E. Roberts
Keyword(s):  
Risc Processor ◽  
Embedded Applications

DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG

2018 ◽  
Vol 6 (4) ◽  
pp. 38
Author(s):  
S. M. BHAGAT ◽  
S. U. BHANDARI ◽  
◽  
Keyword(s):  
Risc Processor

scholarly journals Performance vs. hardware requirements in state-of-the-art automatic speech recognition

2021 ◽  
Vol 2021 (1) ◽  
Author(s):  
Alexandru-Lucian Georgescu ◽  
Alessandro Pappalardo ◽  
Horia Cucu ◽  
Michaela Blott
Keyword(s):  
Speech Recognition ◽  
Automatic Speech Recognition ◽  
State Of The Art ◽  
Decision Makers ◽  
Computing Power ◽  
Trade Off ◽  
Speech Features ◽  
Commercial Applications ◽  
Guided Tour ◽  
Embedded Applications

AbstractThe last decade brought significant advances in automatic speech recognition (ASR) thanks to the evolution of deep learning methods. ASR systems evolved from pipeline-based systems, that modeled hand-crafted speech features with probabilistic frameworks and generated phone posteriors, to end-to-end (E2E) systems, that translate the raw waveform directly into words using one deep neural network (DNN). The transcription accuracy greatly increased, leading to ASR technology being integrated into many commercial applications. However, few of the existing ASR technologies are suitable for integration in embedded applications, due to their hard constrains related to computing power and memory usage. This overview paper serves as a guided tour through the recent literature on speech recognition and compares the most popular ASR implementations. The comparison emphasizes the trade-off between ASR performance and hardware requirements, to further serve decision makers in choosing the system which fits best their embedded application. To the best of our knowledge, this is the first study to provide this kind of trade-off analysis for state-of-the-art ASR systems.

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