A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion

2001 ◽  
Vol 36 (5) ◽  
pp. 846-853 ◽  
Author(s):  
L.G. McIlrath
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Noise ◽  
Cmos Imager

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

scholarly journals Development of a new distributed hybrid seismic-electrical data acquisition station based on system–on-a-programmable-chip technology

2019 ◽  
Author(s):  
Qisheng Zhang ◽  
Wenhao Li ◽  
Feng Guo ◽  
Zhenzhong Yuan ◽  
Shuaiqing Qiao ◽  
...  
Keyword(s):  
Low Power ◽  
Data Acquisition ◽  
High Precision ◽  
Data Transmission ◽  
Dynamic Range ◽  
Low Voltage ◽  
Low Noise ◽  
Transmission Protocol ◽  
Control Board ◽  
Electrical Data

Abstract. In the past few decades, with the continuous advancement of technology, seismic-electrical instruments have developed rapidly. However, complex and harsh exploration environments have put forward higher requirements and severe challenges for traditional geophysical exploration methods and instruments. Therefore, it is extremely urgent to develop new high-precision exploration instruments and data acquisition systems. In this study, a new distributed seismic-electrical hybrid acquisition station is developed using system-on-a-programmable-chip (SoPC) technology. The acquisition station hardware includes an analog board and a main control board. The analog board uses a signal conditioning circuit and a 24-bit analog-to-digital converter (ADS1271) to achieve high-precision data acquisition, while the main control board uses a low-power SoPC chip to enable high-speed stable data transmission. Moreover, the data transmission protocol for the acquisition station was designed, an improved low-voltage differential signaling data transmission technology was independently developed, and a method to enhance the precision of synchronous acquisition was studied in depth. These key technologies, which were developed for the acquisition station, were integrated into the SoPC of the main control board. Testing results indicate that the synchronization precision of the acquisition station is better than 200 ns, and the maximum low-power data transmission speed is 16 Mbps along a 55 m cable. Simultaneously, the developed acquisition station has the advantages of low noise, large dynamic range, low power consumption, etc., and it can achieve high-precision hybrid acquisition of seismic-electrical data.

A Miniaturized Micro-Digital Sun Sensor by Means of Low-Power Low-Noise CMOS Imager

2014 ◽  
Vol 14 (1) ◽  
pp. 96-103 ◽  
Author(s):  
Ning Xie ◽  
Albert J. P. Theuwissen
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Cmos Imager ◽  
Sun Sensor

scholarly journals Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1936
Author(s):  
Luis Miguel Carvalho Freitas ◽  
Fernando Morgado-Dias
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Flicker Noise ◽  
Image Sensor ◽  
Low Noise ◽  
Image Noise ◽  
Frame Rate ◽  
Direct Role ◽  
Sigma Delta

Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

A 4-M Pixel High Dynamic Range, Low-Noise CMOS Image Sensor With Low-Power Counting ADC

2017 ◽  
Vol 64 (8) ◽  
pp. 3199-3205 ◽  
Author(s):  
Cheng Ma ◽  
Yang Liu ◽  
Yang Li ◽  
Quan Zhou ◽  
Xinyang Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Noise ◽  
Power Counting ◽  
High Dynamic
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