A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

1999 ◽  
Vol 34 (10) ◽  
pp. 1395-1399 ◽  
Author(s):  
C.F. Law ◽  
S.S. Rofail ◽  
K.S. Yeo
Keyword(s):  
Low Power ◽  
Parallel Multiplier ◽  
Pass Transistor ◽  
Pass Transistor Logic

scholarly journals Low power 18T pass transistor logic ripple carry adder

2015 ◽  
Vol 12 (6) ◽  
pp. 20150176-20150176 ◽  
Author(s):  
Veeraiyah Thangasamy ◽  
Noor Ain Kamsani ◽  
Mohd Nizar Hamidon ◽  
Shaiful Jahari Hashim ◽  
Zubaida Yusoff ◽  
...  
Keyword(s):  
Low Power ◽  
Ripple Carry Adder ◽  
Pass Transistor ◽  
Pass Transistor Logic

scholarly journals Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

F1000Research ◽  
2022 ◽  
Vol 11 ◽  
pp. 7
Author(s):  
Chinnaiyan Senthilpari ◽  
Rosalind Deena ◽  
Lee Lini
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Computer Aided Design ◽  
Error Correcting Codes ◽  
Low Density ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Low Power Dissipation ◽  
Pass Transistor ◽  
Pass Transistor Logic

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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