A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

1991 ◽  
Vol 26 (3) ◽  
pp. 422-426 ◽  
Author(s):  
A.A. Iranmanesh ◽  
V. Ilderem ◽  
M. Biswal ◽  
B. Bastani
Keyword(s):  
High Performance ◽  
High Density ◽  
Bicmos Technology

HIGH PERFORMANCE ECL-BiCMOS TECHNOLOGY

1993 ◽  
Vol 04 (03) ◽  
pp. 283-299
Author(s):  
T. M. LIU ◽  
R. G. SWARTZ ◽  
T.Y. CHIU
Keyword(s):  
High Speed ◽  
High Performance ◽  
Process Integration ◽  
High Density ◽  
Bipolar Devices ◽  
Bipolar Technology ◽  
Bicmos Technology ◽  
Bipolar Circuit

With the increasing maturity of conventional Bipolar-CMOS (BiCMOS) technologies, a new category of BiCMOS called "ECL-BiCMOS" or high performance BiCMOS technology has emerged. These ECL-BiCMOS technologies offer not only high density CMOS capability, but also feature high speed bipolar devices for emitter couple logic (ECL) and mixed analog/digital applications. Since many process requirements of advanced bipolar technology differ from those of CMOS, to fabricate high speed bipolar devices without compromising CMOS performance is the primary challenge. In this paper, we discuss key process integration issues and review various approaches. In particular, we describe a recently developed half-micron super self-aligned BiCMOS technology. Together with high density/high speed CMOS, multi-GHz communication bipolar circuit results are presented to show the potential of high performance BiCMOS technology.

A 0.8 mu m advanced single poly BiCMOS technology for high density and high performance applications

2002 ◽  
Author(s):  
V. Ilderem ◽  
A. Iranmanesh ◽  
A. Solheim ◽  
L. Lam ◽  
C. Blair ◽  
...  
Keyword(s):  
High Performance ◽  
High Density ◽  
Bicmos Technology

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

scholarly journals A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Voltage Regulation ◽  
High Density ◽  
On Chip

Highly doped and exposed Cu(i)–N active sites within graphene towards efficient oxygen reduction for zinc–air batteries

2016 ◽  
Vol 9 (12) ◽  
pp. 3736-3745 ◽  
Author(s):  
Haihua Wu ◽  
Haobo Li ◽  
Xinfei Zhao ◽  
Qingfei Liu ◽  
Jing Wang ◽  
...  
Keyword(s):  
Oxygen Reduction ◽  
Active Sites ◽  
High Performance ◽  
High Density ◽  
Catalyst Loading ◽  
Zinc Air Batteries

High-density coordination unsaturated copper(i)–nitrogen embedded in graphene demonstrates a high performance and stability in primary zinc–air batteries with ultralow catalyst loading.

A high performance, high density sea of modules FPGA architecture

2002 ◽  
Author(s):  
K. El-Ayat ◽  
S. Kaptanoglu ◽  
R. Chan ◽  
J. Lien ◽  
W. Plants ◽  
...  
Keyword(s):  
High Performance ◽  
High Density ◽  
Fpga Architecture
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