A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver

1996 ◽  
Vol 31 (7) ◽  
pp. 880-889 ◽  
Author(s):  
A. Rofougaran ◽  
J.Y.-C. Chang ◽  
M. Rofougaran ◽  
A.A. Abidi
Keyword(s):  
Direct Conversion ◽  
Wireless Receiver ◽  
Front End ◽  
Rf Front End ◽  
Cmos Rf

Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

2012 ◽  
Vol E95.B (7) ◽  
pp. 2498-2500 ◽  
Author(s):  
Ilku NAM ◽  
Hyunwon MOON ◽  
Doo Hyung WOO
Keyword(s):  
Direct Conversion ◽  
Low Noise ◽  
Front End ◽  
Rf Front End ◽  
Cmos Rf

scholarly journals A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang
Keyword(s):  
Power Consumption ◽  
Flicker Noise ◽  
Analytical Formula ◽  
Direct Conversion ◽  
Low Noise ◽  
Cmos Process ◽  
Passive Mixer ◽  
Dc Offset ◽  
Front End ◽  
Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

2010 ◽  
Vol 31 (2) ◽  
pp. 025006
Author(s):  
Wang Keping ◽  
Wang Zhigong ◽  
Lei Xuemei
Keyword(s):  
Front End ◽  
Rf Front End ◽  
Cmos Rf ◽  
Noise Canceling
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