Digital FIR filters for high speed PRML disk read channels

1995 ◽  
Vol 30 (12) ◽  
pp. 1517-1523 ◽  
Author(s):  
D.J. Pearson ◽  
S.K. Reynolds ◽  
A.C. Megdanis ◽  
S. Gowda ◽  
K.R. Wrenner ◽  
...  
Keyword(s):  
High Speed ◽  
Fir Filters ◽  
Digital Fir Filters

A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS

2003 ◽  
Vol 12 (05) ◽  
pp. 643-654 ◽  
Author(s):  
YONG LIAN
Keyword(s):  
Frequency Response ◽  
High Speed ◽  
Sampling Frequency ◽  
Fir Filters ◽  
Throughput Rate ◽  
Shaping Filter ◽  
Filter Structure ◽  
Frequency Response Masking ◽  
Digital Fir Filters ◽  
Frm Approach

This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

A novel technique for common sub-expression elimination for digital FIR filters using hit and miss transform

2021 ◽  
Vol 174 ◽  
pp. 107793
Author(s):  
A. Kumar ◽  
I. Sharma ◽  
S. Vishwakarma ◽  
L.K. Balyan
Keyword(s):  
Fir Filters ◽  
Novel Technique ◽  
Digital Fir Filters

scholarly journals High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz Mir
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
High Efficiency ◽  
Critical Path ◽  
Fir Filters ◽  
Path Delay ◽  
Look Up Table ◽  
Improved Performance ◽  
Ip Cores ◽  
Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

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