A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces

1995 ◽  
Vol 30 (2) ◽  
pp. 110-119 ◽  
Author(s):  
S. Tedja ◽  
J. Van der Speigel ◽  
H.H. Williams
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Low Noise ◽  
Charge Sampling ◽  
Sensor Interfaces ◽  
Capacitive Detector

A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA

2013 ◽  
Vol 22 (09) ◽  
pp. 1340015 ◽  
Author(s):  
YAJING ZHANG ◽  
WENGAO LU ◽  
GUANNAN WANG ◽  
ZHONGJIAN CHEN ◽  
YACONG ZHANG
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Low Noise ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Analog To Digital Conversion ◽  
Amplifier Design

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

scholarly journals Design of Low Power Low Noise Amplifier using Gm-boosted Technique

2018 ◽  
Vol 9 (3) ◽  
pp. 685 ◽  
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Design Specifications ◽  
Noise Amplifier

This paper presents the development of low noise amplifier integrated circuit using 130nm RFCMOS technology. The low noise amplifier function is to amplify extremely low noise amplifier without adding noise and preserving required signal to a noise ratio. A detailed methodology and analysis that leads to a low power LNA are being discussed throughout this paper. Inductively degenerated and Gm-boosted topology are used to design the circuit. Design specifications are focused for 802.11b/g/n IEEE Wireless LAN Standards with center frequency of 2.4 GHz. The best low noise amplifier provides a power gain (S21) of 19.841 dB with noise figure (NF) of 1.497 dB using the gm-boosted topology while the best low power amplifier drawing 4.19mW power from a 1.2V voltage supply using the inductively degenerated.

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

2018 ◽  
Vol 27 (05) ◽  
pp. 1850068 ◽  
Author(s):  
Hyung Seok Kim ◽  
Hyouk-Kyu Cha
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise ◽  
Two Stage ◽  
Prosthetic Devices ◽  
Transconductance Amplifier ◽  
Cmos Amplifier

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs

2011 ◽  
Vol E94-C (10) ◽  
pp. 1698-1701
Author(s):  
Yang SUN ◽  
Chang-Jin JEONG ◽  
In-Young LEE ◽  
Sang-Gug LEE
Keyword(s):  
Low Power ◽  
Digital Tv ◽  
Low Noise ◽  
On Chip ◽  
Tracking Filter

A low noise and low power device composed of electrode and CD ASIC for neural and other vital signals recording

2021 ◽  
Vol 324 ◽  
pp. 112681
Author(s):  
Jianhui Sun ◽  
Zibin Wang ◽  
Tongxi Wang ◽  
Guozhu Liu ◽  
Jiangwei Tian
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Power Device

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

Tunable Low-Power Low-Noise Amplifier for Healthcare Applications

2021 ◽  
Author(s):  
Rafael Vieira ◽  
Nuno Horta ◽  
Nuno Lourenço ◽  
Ricardo Póvoa
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Healthcare Applications ◽  
Noise Amplifier
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