Soft Error Protection in Safety Critical Embedded Applications: An Overview

An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

Electronics ◽

10.3390/electronics10172101 ◽

2021 ◽

Vol 10 (17) ◽

pp. 2101

Author(s):

Yohan Ko

Keyword(s):

Low Cost ◽

Soft Error ◽

Error Protection ◽

Tolerance Mechanisms ◽

Protection Scheme ◽

Systems Software ◽

Reliability Performance ◽

Design Cost ◽

Embedded Applications ◽

Selection Of

The exponentially increasing occurrence of soft errors makes the optimization of reliability, performance, hardware area, and power consumption one of the main concerns in modern embedded processors. Since the design cost of hardware techniques aimed at improving the reliability of microprocessors is quite expensive for resource-constrained embedded systems, software-level fault tolerance mechanisms have been proposed as an attractive solution for soft error threats. However, many software-level redundancy-based schemes are accompanied by considerable performance overhead, which is not acceptable for many embedded applications. In this work, we have introduced an ultra-low-cost soft error protection scheme for embedded applications, which works based on source-code analysis and identifying critical variables. After identification, these vital variables are adequately protected by placing runtime checks at critical points of execution. Our experimental results based on several applications demonstrate that the proposed scheme can mitigate the failure rate by 47% with negligible performance degradation.

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Partitioned reuse cache for energy-efficient soft-error protection of functional units

2008 IEEE International SOC Conference ◽

10.1109/socc.2008.4641471 ◽

2008 ◽

Author(s):

Kaushal R. Gandhi ◽

Nihar R. Mahapatra

Keyword(s):

Energy Efficient ◽

Soft Error ◽

Error Protection ◽

Functional Units

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Improving Instruction TLB Reliability with Efficient Multi-bit Soft Error Protection

Microelectronics Reliability ◽

10.1016/j.microrel.2018.12.011 ◽

2019 ◽

Vol 93 ◽

pp. 29-38 ◽

Cited By ~ 1

Author(s):

Vahdaneh Kiani ◽

Pedro Reviriego

Keyword(s):

Soft Error ◽

Error Protection ◽

Improving Instruction

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Towards Fully Jitterless Applications: Periodic Scheduling in Multiprocessor MCSs Using a Table-Driven Approach

Applied Sciences ◽

10.3390/app10196702 ◽

2020 ◽

Vol 10 (19) ◽

pp. 6702

Author(s):

Eugenia Ana Capota ◽

Cristina Sorina Stangaciu ◽

Mihai Victor Micea ◽

Daniel-Ioan Curiac

Keyword(s):

Real Time ◽

Multiprocessor Systems ◽

Preemptive Scheduling ◽

Algorithm Performance ◽

Safety Critical ◽

Time Table ◽

Scheduling Method ◽

Embedded Applications ◽

Special Case ◽

Mixed Criticality

In mixed criticality systems (MCSs), the time-triggered scheduling approach focuses on a special case of safety-critical embedded applications which run in a time-triggered environment. Sometimes, for these types of MCSs, perfectly periodical (i.e., jitterless) scheduling for certain critical tasks is needed. In this paper, we propose FENP_MC (Fixed Execution Non-Preemptive Mixed Criticality), a real-time, table-driven, non-preemptive scheduling method specifically adapted to mixed criticality systems which guarantees jitterless execution in a mixed criticality time-triggered environment. We also provide a multiprocessor version, namely, P_FENP_MC (Partitioned Fixed Execution Non-Preemptive Mixed Criticality), using a partitioning heuristic. Feasibility tests are proposed for both uniprocessor and homogenous multiprocessor systems. An analysis of the algorithm performance is presented in terms of success ratio and scheduling jitter by comparing it against a time-triggered and an event-driven method in a non-preemptive context.

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