Design and implementation of high-performance video processor for head-mounted displays

2011 ◽  
Author(s):  
Hou Zuoxun ◽  
Ge Chenyang ◽  
Zhao Wenzhe ◽  
Liu Longjun ◽  
Zheng Nanning
Keyword(s):  
High Performance ◽  
Design And Implementation ◽  
Head Mounted Displays ◽  
Video Processor

Compact high-performance MWIR camera with exposure control and 12-bit video processor

1998 ◽  
Author(s):  
Thomas S. Villani ◽  
Kenneth A. Loesser ◽  
Steve N. Perna ◽  
D. R. McCarthy ◽  
Francis P. Pantuso
Keyword(s):  
High Performance ◽  
Exposure Control ◽  
Video Processor

High Performance Video Processor for Color Television

1984 ◽  
Vol CE-30 (3) ◽  
pp. 278-296
Author(s):  
R. L. Shanley ◽  
L. A. Harwood
Keyword(s):  
High Performance ◽  
Video Processor ◽  
Color Television

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

Sign in / Sign up

Export Citation Format

Share Document