A single-chip audio signal processor for HDTV receiver

1991 ◽  
Vol 37 (3) ◽  
pp. 677-683
Author(s):  
K. Naganawa ◽  
Y. Hori ◽  
S. Yanase ◽  
N. Itoh ◽  
Y. Asano
Author(s):  
K. Naganawa ◽  
Y. Hori ◽  
S. Yanase ◽  
N. Itoh ◽  
Y. Asano

1989 ◽  
Vol 24 (6) ◽  
pp. 1662-1667 ◽  
Author(s):  
K. Kikuchi ◽  
Y. Nukada ◽  
Y. Aoki ◽  
T. Kanou ◽  
Y. Endo ◽  
...  

1984 ◽  
Vol 15 (4) ◽  
pp. 20-28
Author(s):  
Hideo Hara ◽  
Takashi Akazawa ◽  
Yoshimune Hagiwara

Author(s):  
T. Nishitani ◽  
S. Aikoh ◽  
T. Araseki ◽  
K. Ozawa ◽  
R. Maruta

1992 ◽  
Vol 91 (6) ◽  
pp. 3596-3596
Author(s):  
Tod M. Adamson

1989 ◽  
Author(s):  
A. Picco ◽  
J.C. Michalina ◽  
B. Laurier ◽  
D. Fuin ◽  
P. Menut ◽  
...  

1993 ◽  
Vol 03 (02) ◽  
pp. 269-292 ◽  
Author(s):  
MICHAEL PETER KENNEDY ◽  
CHAI WAH WU ◽  
STANLEY PAU ◽  
JAMES TOW

This paper is concerned with exploiting the architecture of a single-chip digital signal processor for integrating piecewise-linear ODEs. We show that DSPs can be usefully applied in the study of Chua's circuit family provided that one chooses a multistep integration algorithm which exploits their unique single-instruction multiply-and-accumulate feature.


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