Real-time PC-based software implementation of H.261 video codec

1997 ◽  
Vol 43 (4) ◽  
pp. 1234-1244 ◽  
Author(s):  
Den-Yuan Hsiau ◽  
Ja-Ling Wu
Keyword(s):  
Real Time ◽  
Video Codec ◽  
Software Implementation

Theoretical basis and software implementation of contour analysis of cardiosignals in real time

1999 ◽  
Vol 33 (1) ◽  
pp. 27-31
Author(s):  
V. A. Kalantar ◽  
A. G. Arakcheev ◽  
V. P. Gundarov
Keyword(s):  
Real Time ◽  
Theoretical Basis ◽  
Software Implementation ◽  
Contour Analysis

Real-time MPEG video codec on a single-chip multiprocessor

1994 ◽  
Author(s):  
Woobin Lee ◽  
Jeremiah Golston ◽  
Robert J. Gove ◽  
Yongmin Kim
Keyword(s):  
Real Time ◽  
Video Codec ◽  
Chip Multiprocessor ◽  
Single Chip

Real time H.263 video codec using parallel DSP

2002 ◽  
Author(s):  
W. Lin ◽  
K.H. Goh ◽  
B.J. Tye ◽  
G.A. Powell ◽  
T. Ohya ◽  
...  
Keyword(s):  
Real Time ◽  
Video Codec

scholarly journals Effective Analysis of an Iterative Median Filter-Hardware and Software Perspective

2019 ◽  
Vol 8 (3) ◽  
pp. 5580-5583
Keyword(s):  
Image Quality ◽  
Real Time ◽  
Median Filter ◽  
Iteration Process ◽  
Software Implementation ◽  
Quality Enhancement ◽  
Image Quality Enhancement ◽  
Key Factor ◽  
Effective Analysis

Image quality enhancement is a very predominant domain of discussion as the complexity of system increases, the software implementation becomes a key factor but it is not always reliable to use the approach for adaptable applications such as medical, military or real time purpose. In order to address such scenarios it is necessary to have a reconfigurable and an adaptable implementation. In this paper we have addressed the hardware modeling of a median filter using double iteration process. The iterative median filter is implemented on an Artix-7 FPGA.

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