Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors-chip design and system implementation

1999 ◽  
Vol 5 (2) ◽  
pp. 376-386 ◽  
Author(s):  
C.B. Kuznia ◽  
J.-M. Wu ◽  
C.-H. Chen ◽  
B. Hoanca ◽  
L. Cheng ◽  
...  
Keyword(s):  
Two Dimensional ◽  
System Implementation ◽  
Chip Design ◽  
Parallel Pipeline ◽  
Pixel Array ◽  
Smart Pixel ◽  
Cellular Logic ◽  
Smart Pixel Array

High-speed image processing on digital smart pixel array

2002 ◽  
Vol 38 (12) ◽  
pp. 590 ◽  
Author(s):  
H. Kawai ◽  
A. Baba ◽  
M. Shibata ◽  
Y. Takeuchi ◽  
T. Komuro ◽  
...  
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Pixel Array ◽  
Smart Pixel ◽  
High Speed Image Processing ◽  
Smart Pixel Array

Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array

1997 ◽  
Author(s):  
Stefan K. Griebel ◽  
M. Richardson ◽  
K. E. Devenport ◽  
Harvard S. Hinton
Keyword(s):  
Experimental Performance ◽  
Pixel Array ◽  
Smart Pixel ◽  
Smart Pixel Array
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