A data flow technique for the efficient design of a class of parallel non-data flow signal processors

1990 ◽  
Vol 38 (12) ◽  
pp. 2162-2173 ◽  
Author(s):  
M. Thaler ◽  
G.S. Moschytz
Keyword(s):  
Data Flow ◽  
Efficient Design ◽  
Flow Signal ◽  
Signal Processors

An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics

2021 ◽  
pp. 1-4
Author(s):  
N. Manoj Kumar ◽  
◽  
G. Saravanan ◽  
D. Shyam Ganesh ◽  
S. Kanimozi ◽  
...  
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Square Root ◽  
Efficient Design ◽  
Verilog Hdl ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Game Plan ◽  
Signal Processors

Duplicate and Accumulate (MAC) is one of the central practices utilized absolutely in signal- controlling and different applications. The multiplier is the major piece of Digital Signal Processors (DSPs). Its cutoff spins around power, LUT use, and surrender pick the presence of a DSP. In like way, there is a need to sort out the drive and give up fit multiplier. In this paper, a 16-digit MAC unit is proposed to utilize an 8-cycle Vedic multiplier and pass on a save snake. A relationship with the current 8-cycle Vedic multiplier utilizing Square-Root (SQR) Carry-select snake (CSLA) is introduced. It is isolated and a standard pack multiplier. The whole technique is done in Verilog HDL. Blend and redirections were finished utilizing Xilinx InDesign Suite 14.5. The proposed game plan accomplishes fundamental improvement in region and suspension. In like manner, an abatement in power around 9.5% is refined.

DFSP: A Data Flow Signal Processor

1986 ◽  
Vol C-35 (1) ◽  
pp. 23-33 ◽  
Author(s):  
Hartimo ◽  
Kronlof ◽  
Simula ◽  
Skytta
Keyword(s):  
Data Flow ◽  
Flow Signal ◽  
Signal Processor
Sign in / Sign up

Export Citation Format

Share Document