Average power reduction techniques for multiple-subcarrier intensity-modulated optical signals

2001 ◽  
Vol 49 (12) ◽  
pp. 2164-2171 ◽  
Author(s):  
R. You ◽  
J.M. Kahn
Circuit World ◽  
2020 ◽  
Vol 47 (1) ◽  
pp. 97-104 ◽  
Author(s):  
Shilpi Birla ◽  
Sudip Mahanti ◽  
Neha Singh

Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.


Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1410
Author(s):  
Mohamed Mounir ◽  
Mohamed B. El_Mashade ◽  
Salah Berra ◽  
Gurjot Singh Gaba ◽  
Mehedi Masud

Several high-speed wireless systems use Orthogonal Frequency Division Multiplexing (OFDM) due to its advantages. 5G has adopted OFDM and is expected to be considered beyond 5G (B5G). Meanwhile, OFDM has a high Peak-to-Average Power Ratio (PAPR) problem. Hybridization between two PAPR reduction techniques gains the two techniques’ advantages. Hybrid precoding-companding techniques are attractive as they require small computational complexity to achieve high PAPR reduction gain. Many precoding-companding techniques were introduced to increasing the PAPR reduction gain. However, reducing Bit Error Rate (BER) and out-of-band (OOB) radiation are more significant than increasing PAPR reduction gain. This paper proposes a new precoding-companding technique to better reduce the BER and OOB radiation than previous precoding-companding techniques. Results showed that the proposed technique outperforms all previous precoding-companding techniques in BER enhancement and OOB radiation reduction. The proposed technique reduces the Error Vector Magnitude (EVM) by 15 dB compared with 10 dB for the best previous technique. Additionally, the proposed technique increases high power amplifier efficiency (HPA) by 11.4%, while the best previous technique increased HPA efficiency by 9.8%. Moreover, our proposal achieves PAPR reduction gain better than the most known powerful PAPR reduction technique with a 99% reduction in required computational complexity.


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