A new pattern jitter free frequency error detector

1989 ◽  
Vol 37 (2) ◽  
pp. 159-163 ◽  
Author(s):  
T. Alberty ◽  
V. Hespelt
Keyword(s):  
Frequency Error ◽  
Error Detector

A multiple guard interval based frequency error detector for OFDM systems

2000 ◽  
Vol 46 (2) ◽  
pp. 363-367 ◽  
Author(s):  
Hyunjae Kim ◽  
Hongku Kang ◽  
Wooncheol Hwang ◽  
Kiseon Kim
Keyword(s):  
Frequency Error ◽  
Ofdm Systems ◽  
Guard Interval ◽  
Error Detector

scholarly journals Low-complexity sparse-aware multiuser detection for large-scale MIMO systems

2021 ◽  
Vol 2021 (1) ◽  
Author(s):  
Rong Ran ◽  
Hayoung Oh
Keyword(s):  
Large Scale ◽  
Mimo Systems ◽  
Minimum Mean Square Error ◽  
Multiple Input Multiple Output ◽  
Low Complexity ◽  
Finite Alphabet ◽  
Multiuser Detectors ◽  
Input Multiple Output ◽  
Error Detector ◽  
Significant Performance

AbstractSparse-aware (SA) detectors have attracted a lot attention due to its significant performance and low-complexity, in particular for large-scale multiple-input multiple-output (MIMO) systems. Similar to the conventional multiuser detectors, the nonlinear or compressive sensing based SA detectors provide the better performance but are not appropriate for the overdetermined multiuser MIMO systems in sense of power and time consumption. The linear SA detector provides a more elegant tradeoff between performance and complexity compared to the nonlinear ones. However, the major limitation of the linear SA detector is that, as the zero-forcing or minimum mean square error detector, it was derived by relaxing the finite-alphabet constraints, and therefore its performance is still sub-optimal. In this paper, we propose a novel SA detector, named single-dimensional search-based SA (SDSB-SA) detector, for overdetermined uplink MIMO systems. The proposed SDSB-SA detector adheres to the finite-alphabet constraints so that it outperforms the conventional linear SA detector, in particular, in high SNR regime. Meanwhile, the proposed detector follows a single-dimensional search manner, so it has a very low computational complexity which is feasible for light-ware Internet of Thing devices for ultra-reliable low-latency communication. Numerical results show that the the proposed SDSB-SA detector provides a relatively better tradeoff between the performance and complexity compared with several existing detectors.

scholarly journals Design of Cut off-Frequency Fixing Filters by Error Compensation of MAXFLAT FIR Filters

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 553
Author(s):  
Daewon Chung ◽  
Woon Cho ◽  
Inyeob Jeong ◽  
Joonhyeon Jeon
Keyword(s):  
Closed Form ◽  
Error Compensation ◽  
Finite Impulse Response ◽  
Cutoff Frequency ◽  
Closed Form Solution ◽  
Form Solution ◽  
Fir Filters ◽  
Frequency Error ◽  
Computationally Efficient ◽  
Filter Type

Maximally-flat (MAXFLAT) finite impulse response (FIR) filters often face a problem of the cutoff-frequency error due to approximation of the desired frequency response by some closed-form solution. So far, there have been plenty of efforts to design such a filter with an arbitrarily specified cut off-frequency, but this filter type requires extensive computation and is not MAXFLAT anymore. Thus, a computationally efficient and effective design is needed for highly accurate filters with desired frequency characteristics. This paper describes a new method for designing cutoff-frequency-fixing FIR filters through the cutoff-frequency error compensation of MAXFLAT FIR filters. The proposed method provides a closed-form Chebyshev polynomial containing a cutoff-error compensation function, which can characterize the “cutoff-error-free” filters in terms of the degree of flatness for a given order of filter and cut off-frequency. This method also allows a computationally efficient and accurate formula to directly determine the degree of flatness, so that this filter type has a flat magnitude characteristic both in the passband and the stopband. The remarkable effectiveness of the proposed method in design efficiency and accuracy is clearly demonstrated through various examples, indicating that the cutoff-fixing filters exhibit amplitude distortion error of less than 10−14 and no cut off-frequency error. This new approach is shown to provide significant advantages over the previous works in design flexibility and accuracy.

Error Compensation Software to Remove the Low-Frequency Error of Aluminum Freeform Mirror for an Infrared Off-Axis Telescope

2021 ◽  
Vol 38 (5) ◽  
pp. 329-336
Author(s):  
Tae-Geun Ji ◽  
Dae Wook Kim ◽  
Woojin Park ◽  
Soojong Pak ◽  
Byeongjoon Jeong ◽  
...  
Keyword(s):  
Error Compensation ◽  
Low Frequency ◽  
Frequency Error

scholarly journals An Accurate DDS Method Using Compound Frequency Tuning Word and Its FPGA Implementation

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 330 ◽  
Author(s):  
Yuqing Hou ◽  
Changlong Li ◽  
Sheng Tang
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Low Cost ◽  
Atomic Clock ◽  
Frequency Error ◽  
Frequency Synthesis ◽  
Direct Digital Synthesizer ◽  
Low Power Dissipation ◽  
Conversion Time ◽  
The Stability

Because of its high resolution, low cost, small volume, low power dissipation and less conversion time consumption, the direct digital synthesizer (DDS) method has been applied more and more in the fields of frequency synthesis and signal generation. However, only a limited number of precise frequency signals can be synthesized by the traditional DDS, for the reason that its accumulator modulus is fixed, and its frequency tuning word must be integer. In this paper, a precise DDS method using compound frequency tuning word is proposed, which improves the accuracy of synthesized signals at any frequency points on the premise of guaranteeing the stability of synthesized signals. In order to verify the effectiveness of the new method, a DDS frequency synthesizer based on FPGA is designed and implemented. Taking the rubidium atomic clock PRS10 as standard frequency source, the experiments shows that the frequency stability of the synthesized signal is better than 8.0 × 10−12/s, the relative frequency error is less than 4.8 × 10−12, and that the frequency accuracy is improved by three orders of magnitude compared with the traditional DDS method.

Implementation of a high speed time resolved error detector utilising a high speed FPGA

2011 ◽  
Author(s):  
John A. O'Dowd ◽  
Vivian M. Bessler ◽  
Selwan K. Ibrahim ◽  
Anthony J. Walsh ◽  
F. H. Peters ◽  
...  
Keyword(s):  
High Speed ◽  
Time Resolved ◽  
Error Detector

scholarly journals Load Frequency Control in a Multi-Area Deregulated Power System with BBBC-based Discrete Fractional Order Control Scheme

2020 ◽  
Vol 15 ◽  
Keyword(s):  
Power System ◽  
Frequency Control ◽  
Big Bang ◽  
Load Frequency Control ◽  
Frequency Error ◽  
Area Control Error ◽  
Load Frequency ◽  
Deregulated Power System ◽  
Control Scheme ◽  
Big Crunch

Load frequency control (LFC) for multi-area restructured power system using discrete controlscheme has been suggested in this paper. The proposed LFC scheme utilizes synchronously measured dataof frequency and tie-line power to calculate area control error (ACE). A discrete non-integer proportionalintegral derivative controller (D-FOPID) has been used to derive frequency error to zero. Two-area thermaland four-area hydro thermal deregulated power system has been used to investigate various LFC issues. Theoptimal factors of D-FOPID have been obtained using big bang big crunch (BBBC) algorithm. The systemresults under MATLAB/Simulink validate that D-FOPID effectively work under different types of contractscenarios. D-FOPID performance has also been compared to discrete proportional integral derivativecontroller (D-PID). Further the compliance with control standards of North American electric reliabilitycouncil (NERC) has also been ensured for both the controller.

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