Utilizing Hopfield neural networks and an improved simulated annealing procedure for design optimization of electromagnetic devices

1993 ◽  
Vol 29 (6) ◽  
pp. 2404-2406 ◽  
Author(s):  
O.A. Mohammed ◽  
R.S. Merchant ◽  
F.G. Uler
Keyword(s):  
Neural Networks ◽  
Simulated Annealing ◽  
Design Optimization ◽  
Hopfield Neural Networks ◽  
Electromagnetic Devices ◽  
Annealing Procedure ◽  
Simulated Annealing Procedure

Design optimization of electromagnetic devices using artificial neural networks

1992 ◽  
Vol 28 (5) ◽  
pp. 2805-2807 ◽  
Author(s):  
O.A. Mohammed ◽  
D.C. Park ◽  
F.G. Uler ◽  
C. Ziqiang
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Design Optimization ◽  
Electromagnetic Devices ◽  
Artificial Neural

Molecular dynamics simulations reveal how graphene oxide stabilizes and activates lipase in an anhydrous gas

2019 ◽  
Vol 21 (45) ◽  
pp. 25425-25430 ◽  
Author(s):  
Zhongwang Fu ◽  
Weina Xu ◽  
Gong Chen ◽  
Zheyu Wang ◽  
Diannan Lu ◽  
...  
Keyword(s):  
Molecular Dynamics ◽  
Graphene Oxide ◽  
Simulated Annealing ◽  
Molecular Dynamics Simulations ◽  
Md Simulations ◽  
Candida Antarctica ◽  
Lipase B ◽  
Annealing Procedure ◽  
Dynamics Simulations ◽  
Simulated Annealing Procedure

The interaction between Candida antarctica lipase B (CALB) and graphene oxide (GO) in an anhydrous gas was studied using molecular dynamics (MD) simulations augmented with a simulated annealing procedure to accelerate relaxation towards equilibrium.

Test Pattern Generation of VLSI Circuits Using Hopfield Neural Networks

2010 ◽  
Vol 29-32 ◽  
pp. 1034-1039
Author(s):  
Zhong Liang Pan ◽  
Ling Chen ◽  
Guang Zhao Zhang
Keyword(s):  
Neural Networks ◽  
Simulated Annealing ◽  
Energy Function ◽  
Digital Circuits ◽  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Hopfield Neural Networks ◽  
Test Pattern Generation ◽  
Chaotic Simulated Annealing

A new test pattern generation method for the stuck-at faults in VLSI circuits is presented in this paper, the method uses Hopfield neural networks and chaotic simulated annealing. The Hopfield neural network corresponding to a digital circuit is built, the test patterns of faults in digital circuits are produced by computing the optima of the energy function. A chaotic simulated annealing algorithm is designed, which combines the features of chaotic systems and conventional simulated annealing, it is able to take the advantages of the stochastic properties and global search ability of chaotic system. The algorithm is used to compute the optima of the energy function of neural networks in order to produce the test patterns of faults. Experimental results show that the test pattern generation method proposed in this paper can produce the test patterns in short time for both single stuck-at faults and multiple stuck-at faults in digital circuits.

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