Translation-lookaside buffer consistency

Computer ◽  
1990 ◽  
Vol 23 (6) ◽  
pp. 26-36 ◽  
Author(s):  
P.J. Teller
Keyword(s):  
Translation Lookaside Buffer

scholarly journals REDUCING MIGRATION-INDUCED MISSES IN AN OVER-SUBSCRIBED MULTIPROCESSOR SYSTEM

2013 ◽  
Vol 23 (01) ◽  
pp. 1350006
Author(s):  
SAJJID REZA ◽  
GREGORY T. BYRD
Keyword(s):  
Load Balancing ◽  
Multiprocessor System ◽  
Performance Impact ◽  
Server Consolidation ◽  
Translation Lookaside Buffer ◽  
Context Switch ◽  
L2 Cache ◽  
Virtual Desktop ◽  
Multicore Chips ◽  
Virtual Desktop Infrastructure

In a large multiprocessor server platform using multicore chips, the scheduler often migrates a thread or process, in order to achieve better load balancing or ensure fairness among competing scheduling entities. Each migration incurs a severe performance impact from the loss of cache and Translation Lookaside Buffer (TLB) footprints and subsequent higher cache misses and page walks. Such impact is likely to be more severe in virtualized environments, where high over-subscription of CPUs is very common for server consolidation workloads or virtual desktop infrastructure deployment, causing frequent migrations and context switches. We demonstrate the performance benefit of preserving a portion of L2 cache—in particular, MRU cache lines—and warming the destination L2 cache by prefetching those cache lines under different migration scenarios. We observed a 1.5-27% reduction in CPI (cycles per instruction) following a migration. We also study the effectiveness of preserving TLB entries over a context switch or migration.

A 4 ns BiCMOS translation-lookaside buffer

1990 ◽  
Author(s):  
L. Tamura ◽  
T.-S. Yang ◽  
D. Wingard ◽  
M. Horowitz ◽  
B. Wooley
Keyword(s):  
Translation Lookaside Buffer

scholarly journals Translation lookaside buffer management

2019 ◽  
pp. 20-24
Author(s):  
Y. I. Klimiankou
Keyword(s):  
Simple Model ◽  
Memory Management ◽  
Buffer Management ◽  
Translation Lookaside Buffer ◽  
Physical Address

This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management subsystem of the OS kernel on the example of the IA-32 platform and propose a simple model of complete and consistent policy of TLB management. This model can be used as a foundation for memory management subsystems design and verification.

LPE: Locality-based Dead Prediction in Exclusive TLB for Large Coverage

2021 ◽  
pp. 2150292
Author(s):  
Jing Yan ◽  
Yujuan Tan ◽  
Zhulin Ma ◽  
Jingcheng Liu ◽  
Xianzhang Chen ◽  
...  
Keyword(s):  
Computer Architecture ◽  
Memory Performance ◽  
Memory Systems ◽  
Translation Lookaside Buffer ◽  
Hit Rate ◽  
Spatial Locality ◽  
Total Latency ◽  
Long Time ◽  
Multi Level ◽  
Temporal And Spatial

Translation lookaside buffer (TLB) is critical to modern multi-level memory systems’ performance. However, due to the limited size of the TLB itself, its address coverage is limited. Adopting a two-level exclusive TLB hierarchy can increase the coverage [M. Swanson, L. Stoller and J. Carter, Increasing TLB reach using superpages backed by shadow memory, 25th Annual Int. Symp. Computer Architecture (1998); H.P. Chang, T. Heo, J. Jeong and J. Huh Hybrid TLB coalescing: Improving TLB translation coverage under diverse fragmented memory allocations, ACM SIGARCH Comput. Arch. News 45 (2017) 444–456] to improve memory performance. However, after analyzing the existing two-level exclusive TLBs, we find that a large number of “dead” entries (they will have no further use) exist in the last-level TLB (LLT) for a long time, which occupy much cache space and result in low TLB hit-rate. Based on this observation, we first propose exploiting temporal and spatial locality to predict and identify dead entries in the exclusive LLT and remove them as soon as possible to leave room for more valid data to increase the TLB hit rates. Extensive experiments show that our method increases the average hit rate by 8.67%, to a maximum of 19.95%, and reduces total latency by an average of 9.82%, up to 24.41%.

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