Soft-error-immune switched-load-resistor memory cell

1988 ◽  
Vol 35 (12) ◽  
pp. 2094-2100 ◽  
Author(s):  
N. Homma ◽  
T. Nakamura ◽  
T. Hayashida ◽  
M. Matsumoto ◽  
K. Nakazato ◽  
...  
Keyword(s):  
Memory Cell ◽  
Soft Error ◽  
Load Resistor

A 6ns 4Kb bipolar RAM using switched load resistor memory cell

1979 ◽  
Author(s):  
M. Inadachi ◽  
N. Homma ◽  
K. Yamaguchi ◽  
T. Ikeda ◽  
H. Higuchi
Keyword(s):  
Memory Cell ◽  
Load Resistor

CMOS/SOS High Soft-Error Threshold Memory Cell

1985 ◽  
Vol 32 (6) ◽  
pp. 4155-4158 ◽  
Author(s):  
Fu-Lung Hsueh ◽  
Louis S. Napoli
Keyword(s):  
Memory Cell ◽  
Soft Error ◽  
Error Threshold

An independent dual gate SOI FinFET soft-error resilient memory cell

2014 ◽  
Author(s):  
N. Eftaxiopoulos ◽  
N. Axelos ◽  
G. Zervakis ◽  
K. Tsoumanis ◽  
K. Pekmestzi
Keyword(s):  
Memory Cell ◽  
Soft Error ◽  
Error Resilient ◽  
Dual Gate

scholarly journals Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 33
Author(s):  
Bharathi Raj Muthu ◽  
Ewins Pon Pushpa ◽  
Vaithiyanathan Dhandapani ◽  
Kamala Jayaraman ◽  
Hemalatha Vasanthakumar ◽  
...  
Keyword(s):  
Soft Errors ◽  
Memory Cell ◽  
Soft Error ◽  
Access Time ◽  
Electronic Systems ◽  
Memory Cells ◽  
Noise Margin ◽  
Sram Cell ◽  
Driver Circuit ◽  
Radiation Hardened

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

scholarly journals Design And Analysis Of RHBD Memory Cells And 4x4 RHBD 10T Memory Cell Architecture

2019 ◽  
Vol 8 (10) ◽  
pp. 4232-4237
Keyword(s):  
Supply Voltage ◽  
Memory Cell ◽  
Cmos Technology ◽  
Soft Error ◽  
Cmos Process ◽  
Memory Cells ◽  
Process Technology ◽  
Aerospace Applications ◽  
Cadence Tool ◽  
Layout Area

CMOS technology plays an important role in the modern electronics world. CMOS technology also plays significant role in aerospace applications. To store data, memories are widely used as the medium in aerospace applications. SRAM cells are the memories made by the CMOS technology. The most vital issues faced by memories are due to single event upsets (SEUs) which are induced by radiation particles. The SEU’s due to increase in densities and SEU’s. There is a decrease in critical charge and supply voltage in CMOS process technology. There is a need for a technique which can to tolerate these SEU’s in such aerospace applications. Which are in the environment of complex celestial radiation? The technique which is considered for such environment is radiation-hardened by design (RHBD) with soft error robustness. This paper aims at is proposing an area efficient and high reliable RHBD memory cell for the above said application using 45nm technology in Cadence Tool. Depending on power, write/read time, the layout area of 14T, 12T and 10T RHBD memory cells and their performance on power for read/write operations are observed. A comparative study is also done on these memory cells based the parameters considered.

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