Soft error protection using asymmetric response latches

1991 ◽  
Vol 38 (6) ◽  
pp. 1555-1557 ◽  
Author(s):  
H.T. Weaver ◽  
W.T. Corbett ◽  
J.M. Pimbley
Keyword(s):  
Soft Error ◽  
Error Protection ◽  
Asymmetric Response

Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core

IEEE Micro ◽  
2013 ◽  
Vol 33 (4) ◽  
pp. 56-65 ◽  
Author(s):  
Lukasz G. Szafaryn ◽  
Brett H. Meyer ◽  
Kevin Skadron
Keyword(s):  
Soft Error ◽  
Error Protection ◽  
Processor Core

scholarly journals An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2101
Author(s):  
Yohan Ko
Keyword(s):  
Low Cost ◽  
Soft Error ◽  
Error Protection ◽  
Tolerance Mechanisms ◽  
Protection Scheme ◽  
Systems Software ◽  
Reliability Performance ◽  
Design Cost ◽  
Embedded Applications ◽  
Selection Of

The exponentially increasing occurrence of soft errors makes the optimization of reliability, performance, hardware area, and power consumption one of the main concerns in modern embedded processors. Since the design cost of hardware techniques aimed at improving the reliability of microprocessors is quite expensive for resource-constrained embedded systems, software-level fault tolerance mechanisms have been proposed as an attractive solution for soft error threats. However, many software-level redundancy-based schemes are accompanied by considerable performance overhead, which is not acceptable for many embedded applications. In this work, we have introduced an ultra-low-cost soft error protection scheme for embedded applications, which works based on source-code analysis and identifying critical variables. After identification, these vital variables are adequately protected by placing runtime checks at critical points of execution. Our experimental results based on several applications demonstrate that the proposed scheme can mitigate the failure rate by 47% with negligible performance degradation.

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