High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits

1999 ◽  
Vol 46 (8) ◽  
pp. 1733-1741 ◽  
Author(s):  
G. Dambrine ◽  
J.-P. Raskin ◽  
F. Danneville ◽  
D. Vanhoenackel Janvier ◽  
J.-P. Colinge ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Frequency ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Rf Integrated Circuits ◽  
Noise Parameters

Silicon-On-Insulator-Based Technology MOSFET : Prospects For Application to Low Noise RF Integrated Circuits

1998 ◽  
Author(s):  
G. Dambrine ◽  
J.P. Raskin ◽  
F. Danneville ◽  
D. Vanhoenacker ◽  
J.P. Colinge ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Rf Integrated Circuits

Optimizing SiGe HBTs technology using small-signal and high frequency noise device's modeling

2004 ◽  
Vol 809 ◽  
Author(s):  
J.G Tartarin ◽  
G. Cibiel ◽  
A. Monroy ◽  
V. Le Goascoz ◽  
J. Graffeuil
Keyword(s):  
Technological Process ◽  
High Frequency ◽  
Low Noise ◽  
Rapid Expansion ◽  
Base Layer ◽  
Frequency Noise ◽  
Small Signal ◽  
Technological Parameters ◽  
High Frequency Noise ◽  
Noise Parameters

ABSTRACTThe rapid expansion of SiGe technologies during the last decade essentially due to civil telecommunication's applications have led Si/SiGe based heterojunction bipolar transistors (HBTs) to excellent performance levels, allowing high frequency low noise circuit designs such as linear low noise amplifiers( RF noise) or also low-phase noise oscillators (LF noise). Among these technologies, the SiGe BiCMOS one integrates digital and RF functions on the same chip. Fast improvements of the technological process have been performed thanks to large efforts allowed to characterization and modeling of the devices. We have investigated on the influence of technological parameters such as Germanium profile, doping level and thickness of the base layer (5 different wafers) on the dynamic and high frequency noise performances to converge towards the optimum technological process (now available with the BiCMOS6G processed by ST microelectronics). We made use of scattering parameters [S] measurements on the devices to extract the electrical parameters of our small signal model. The high frequency noise parameters based on the electrical model (with noise sources added to the junction, resistances) are simulated and compared with the measured noise parameters of the devices. The four noise parameters (Fmin, Rn, and complex Γopt) measurements have been performed from 1 GHz to 12 GHz, and the dynamic S parameters measurements have been realized in the 40 MHz-40 GHz range. These models have been used to enable the identification of the limiting parameters on the dynamic performances and on the high frequency noise parameters.

scholarly journals A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 785
Author(s):  
Juan L. Castagnola ◽  
Fortunato C. Dualibe ◽  
Agustín M. Laprovitta ◽  
Hugo García-Vázquez
Keyword(s):  
Integrated Circuits ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Optimization Approach ◽  
Scattering Parameters ◽  
Rf Integrated Circuits ◽  
Design And Optimization ◽  
Noise Amplifier

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

A new method of fluxgate signal extraction

2017 ◽  
Vol 2017 (45) ◽  
pp. 83-89
Author(s):  
A.A. Marusenkov ◽  
Keyword(s):  
High Frequency ◽  
Second Harmonic ◽  
Excitation Frequency ◽  
Low Noise ◽  
Measuring System ◽  
Signal Extraction ◽  
Fluxgate Magnetometer ◽  
New Approach ◽  
Average Value ◽  
The Time Domain

Using dedicated high-frequency measuring system the distribution of the Barkhausen jumps intensity along a reversal magnetization cycle was investigated for low noise fluxgate sensors of various core shapes. It is shown that Barkhausen (reversal magnetization) noise intensity is strongly inhomogeneous during an excitation cycle. In the traditional second harmonic fluxgate magnetometers the signals are extracted in the frequency domain, as a result, some average value of reversal magnetization noises is contributed to the output signals. In order to fit better the noise shape and minimize its transfer to the magnetometer output the new approach for demodulating signals of these sensors is proposed. The new demodulating method is based on information extraction in the time domain taking into account the statistical properties of cyclic reversal magnetization noises. This approach yields considerable reduction of the fluxgate magnetometer noise in comparison with demodulation of the signal filtered at the second harmonic of the excitation frequency.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

Ultra-Low Noise Schottky Junction Tri-Gate Silicon Nanowire FET on Bonded Silicon-on-Insulator Substrate

2021 ◽  
Vol 42 (4) ◽  
pp. 469-472
Author(s):  
Yingtao Yu ◽  
Si Chen ◽  
Qitao Hu ◽  
Paul Solomon ◽  
Zhen Zhang
Keyword(s):  
Silicon Nanowire ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Schottky Junction ◽  
Ultra Low Noise ◽  
Insulator Substrate

scholarly journals Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

2021 ◽  
pp. 1-7
Author(s):  
K. Parow-Souchon ◽  
D. Cuadrado-Calle ◽  
S. Rea ◽  
M. Henry ◽  
M. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Millimeter Wave ◽  
Impedance Matching ◽  
Wave Impedance ◽  
Low Noise ◽  
Device Performance ◽  
Interface Circuits ◽  
Interface Circuit ◽  
Noise Amplifier

Abstract Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

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