0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

1998 ◽  
Vol 45 (3) ◽  
pp. 737-742 ◽  
Author(s):  
M. Saito ◽  
M. Ono ◽  
R. Fujimoto ◽  
H. Tanimoto ◽  
N. Ito ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Low Voltage Operation

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

scholarly journals A Fast ALU Design in CMOS for Low Voltage Operation

VLSI Design ◽  
2002 ◽  
Vol 14 (4) ◽  
pp. 315-327 ◽  
Author(s):  
A. Srivastava ◽  
D. Govindarajan
Keyword(s):  
Delay Time ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Substrate Bias ◽  
Back Gate ◽  
Low Voltage Operation ◽  
Logical Operations ◽  
Ripple Carry Adder ◽  
Speed Advantage

A high-speed 4-bit ALU has been designed for 1 V operation to demonstrate the usefulness of the back-gate forward substrate bias (BGFSB) method in 1.2 μm N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations - four arithmetic and four logical operations. The BGFSB voltage has been limited to |0.4| V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2–2.5 is obtained with BGFSB over the conventional design.

scholarly journals A design of low voltage OPAMP using split-length transistors

2014 ◽  
Vol 17 (1) ◽  
pp. 62-70
Author(s):  
Khanh Trung Le ◽  
Tu Trong Bui ◽  
Hung Duc Le ◽  
Kha Cong Pham
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Feedback Systems ◽  
Advanced Technique ◽  
Low Voltage Operation ◽  
Feedback Compensation ◽  
Indirect Feedback ◽  
Low Supply Voltage

In the paper, we present a design of a low voltage Operation Amplifier (OPAMP) circuit using split-length transistors. Indirect feedback compensation is an advanced technique used to stabilize the operation of an OPAMP. Cascode transistors are usually implemented for indirect feedback systems. However, these transistors are not suitable for low voltage design. In this study, we have taken advantage of split-length transistors and indirect feedback compensation technique to design a high performance OPAMP. As a result, the OPAMP operates not only at low supply voltage but also at high frequency. The OPAMP has been designed and fabricated in a 0.18um CMOS technology. This OPAMP achieves 100 dB gain, 90 MHz unity gain frequency and 60 degrees phase margin at 2 V supply voltage.

scholarly journals A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2108
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Fully Integrated ◽  
Low Voltage Operation ◽  
Error Amplifier ◽  
Ldo Regulator

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

Sub-Volt Fully Balanced Differential Difference Amplifier

2014 ◽  
Vol 24 (01) ◽  
pp. 1550005 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Spyridon Vlassis ◽  
Costas Psychalinos ◽  
Tomasz Kulej
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Voltage Range ◽  
State Variable ◽  
Low Voltage Operation ◽  
Differential Difference Amplifier ◽  
Simulation Results ◽  
State Variable Filter

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

0.3-μm mixed analog/digital CMOS technology for low-voltage operation

1994 ◽  
Vol 41 (10) ◽  
pp. 1837-1842 ◽  
Author(s):  
T. Ishii ◽  
M. Miyamoto ◽  
R. Nagai ◽  
T. Nishida ◽  
K. Seki
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Digital Cmos ◽  
Low Voltage Operation

scholarly journals Ultra-Low-Voltage CMOS-Based Current Bleeding Mixer with High LO-RF Isolation

2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Gim Heng Tan ◽  
Roslina Mohd Sidek ◽  
Harikrishnan Ramiah ◽  
Wei Keat Chong ◽  
De Xing Lioe
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Third Order ◽  
Chip Area ◽  
Integrated Inductors ◽  
Low Voltage Operation ◽  
Dc Power ◽  
Current Bleeding ◽  
Intercept Point

This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm2.

scholarly journals Adaptive Spiking Sensor System Based on CMOS Memristors Emulating Long and Short-Term Plasticity of Biological Synapses for Industry 4.0 Applications

2021 ◽  
Vol 88 (s1) ◽  
pp. s114-s119
Author(s):  
Hamam Abd ◽  
Andreas König
Keyword(s):  
Industry 4.0 ◽  
New Technologies ◽  
Low Voltage ◽  
Leading Edge ◽  
Cmos Technology ◽  
Self Healing ◽  
Short Term ◽  
Technology Scaling ◽  
Short Term Plasticity ◽  
Low Voltage Operation

Abstract A conventional analog to digital converter (ADC) faces many issues with leading-edge technologies due to noise, manufacturing deviations, signal swings, etc. Thus, we pursue to design an adaptive spiking neural ADC (SN-ADC) with promising features, e.g., robust to noise, low-power, technology scaling issues, and low-voltage operation. Therefore, our approach promises to be technology agnostic, i.e., effectively translatable to aggressive new technologies. It supports machine learning and self-x (self-calibration, self-healing) that needs for industry 4.0 and the internet of things (IoTs). In this work, we design an adaptive spike-to-rank coding (ASRC), which is the main part of the spiking neural ADC. The ASRC is based on CMOS memristors emulating short-term plasticity (STP) and long-term plasticity (LTP) biological synapses. The proposed ASRC compensates deviations by adapting the weights of the synapses. Also, ASRC is designed using XFAB 0.35 μm CMOS technology and Cadence design tools. In addition, ASRC is simulated to test its performance in the temperature range (−40°C to 85°C).

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