A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

1990 ◽  
Vol 37 (9) ◽  
pp. 2052-2057 ◽  
Author(s):  
K. Terada ◽  
T. Ishijima ◽  
T. Kubota ◽  
M. Sakao
Keyword(s):  
Silicon Layer ◽  
Epitaxial Silicon ◽  
Epitaxial Silicon Layer

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

1987 ◽  
Author(s):  
T. Kubota ◽  
T. Ishijima ◽  
M. Sakao ◽  
K. Terada ◽  
T. Hamaguchi ◽  
...  
Keyword(s):  
Silicon Layer ◽  
Soft Error ◽  
Epitaxial Silicon ◽  
Epitaxial Silicon Layer

scholarly journals Влияние твердофазной рекристаллизации с двойной имплантацией на плотность структурных дефектов в ультратонких слоях кремния на сапфире

2019 ◽  
Vol 61 (12) ◽  
pp. 2349
Author(s):  
С.Д. Федотов ◽  
В.Н. Стаценко ◽  
Н.Н. Егоров ◽  
С.А. Голубков
Keyword(s):  
Defect Density ◽  
Solid Phase ◽  
Silicon Layer ◽  
Modern Method ◽  
Structural Quality ◽  
Technological Problem ◽  
Recrystallization Process ◽  
Epitaxial Silicon ◽  
Near Surface ◽  
Epitaxial Silicon Layer

The main technological problem in the manufacture of electronics on silicon-on-sapphire (SOS) wafers is the high density of defects in the epitaxial silicon layer. The modern method of obtaining ultrathin SOS wafers using solid-phase epitaxial recrystallization (SPER) and pyrogenic thinning that significantly reduce the defect density in these layers. Nevertheless, the influence of the defect density in submicron SOS layers on the structural quality of ultrathin SOS layers remains unclear. In this work, ultrathin (100 nm) SOS wafers were obtained by SPER of submicron (300 nm) SOS wafers with different structural quality. The crystallinity of 300 nm layers before the recrystallization process and ultrathin layers was determined by XRD and TEM. It was found that the smallest values of the FWHM 0.19-0.20° were observed for the ultrathin SOS layers obtained on the basis of 300 nm SOS wafers with the best structural quality. It was shown that the structural perfect near-surface Si layer, which serves as a seed layer in SPER process, and the double implantation regime allow to reduce the linear defect density in the ultrathin SOS layers by ~ 1×104 cm-1.

A New CMOS Structure Using a Transistor on a Lateral Epitaxial Silicon Layer

1988 ◽  
Author(s):  
T. Ishijima ◽  
K. Terada ◽  
T. Kubota ◽  
M. Sakao ◽  
T. Hamaguchi ◽  
...  
Keyword(s):  
Silicon Layer ◽  
Epitaxial Silicon ◽  
Epitaxial Silicon Layer

A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching

2003 ◽  
Vol 765 ◽  
Author(s):  
M. Q. Huda ◽  
K. Sakamoto
Keyword(s):  
Structural Damage ◽  
Low Dose ◽  
Silicon Layer ◽  
Chemical Vapor ◽  
Selective Etching ◽  
Epitaxial Silicon ◽  
Structural Recovery ◽  
Epitaxial Silicon Layer ◽  
Order Of Magnitude ◽  
Polysilicon Layer

AbstractA process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700°C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420°C was usedfor structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.

A low-gate-leakage-current GaAs MESFET with a thin epitaxial silicon layer

1991 ◽  
Vol 12 (6) ◽  
pp. 324-326 ◽  
Author(s):  
J.C. Costa ◽  
T.J. Miller ◽  
Z. Abid ◽  
F. Williamson ◽  
B.A. Bernhardt ◽  
...  
Keyword(s):  
Leakage Current ◽  
Silicon Layer ◽  
Gate Leakage Current ◽  
Epitaxial Silicon ◽  
Gate Leakage ◽  
Gaas Mesfet ◽  
Epitaxial Silicon Layer

scholarly journals Маска на основе эпитаксиального слоя Si для самокаталитического роста нитевидных нанокристаллов на подложках GaAs (111)B и (100)

2020 ◽  
Vol 46 (4) ◽  
pp. 11
Author(s):  
Е.А. Емельянов ◽  
А.Г. Настовьяк ◽  
М.О. Петрушков ◽  
М.Ю. Есин ◽  
Т.А. Гаврилова ◽  
...  
Keyword(s):  
Molecular Beam Epitaxy ◽  
Molecular Beam ◽  
Silicon Layer ◽  
Vacuum System ◽  
Epitaxial Silicon ◽  
Spectral Ellipsometry ◽  
Single Wave ◽  
Force Microscopy ◽  
Epitaxial Silicon Layer ◽  
Gaas Nanowire

GaAs nanowire (NW) self-catalyzed growth on GaAs (111) B and GaAs (100) substrates was carried out by molecular beam epitaxy. A mask for the self-catalyzed NW growth was created by oxidizing an epitaxial silicon layer grown on the GaAs surface by molecular beam epitaxy (MBE). Silicon oxidation was realized in an atmosphere of purified air under normal conditions without moving the structures out from the vacuum system volume of the molecular beam epitaxy chamber. The oxidation process of a silicon layer was studied using single-wave and spectral ellipsometry and the surface morphology of oxidized silicon was studied by atomic force microscopy. Substrates with NWs were studied by scanning electron microscopy. The NW density was demonstrated to be 2.6•107 cm-2 and 3•107 cm-2 for (111)B and (100), respectively.

Unpinned GaAs Schottky barriers with an epitaxial silicon layer

1991 ◽  
Vol 70 (4) ◽  
pp. 2173-2184 ◽  
Author(s):  
J. C. Costa ◽  
T. J. Miller ◽  
F. Williamson ◽  
M. I. Nathan
Keyword(s):  
Silicon Layer ◽  
Schottky Barriers ◽  
Epitaxial Silicon ◽  
Epitaxial Silicon Layer
Sign in / Sign up

Export Citation Format

Share Document