Analysis of new high-voltage bipolar Silicon-On-Insulator transistor with fully depleted collector

1995 ◽  
Vol 42 (1) ◽  
pp. 172-177 ◽  
Author(s):  
T. Arnborg ◽  
A. Litwin
Keyword(s):  
High Voltage ◽  
Silicon On Insulator ◽  
Fully Depleted

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors

2015 ◽  
Vol 118 (18) ◽  
pp. 184504 ◽  
Author(s):  
C. Navarro ◽  
M. Bawedin ◽  
F. Andrieu ◽  
B. Sagnes ◽  
F. Martinez ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Short Channel ◽  
Fully Depleted

Large Injection Velocities in Highly Scaled, Fully Depleted Silicon on Insulator Transistors

2021 ◽  
pp. 1-1
Author(s):  
Yu-Hung Liao ◽  
Khandker Akif Aabrar ◽  
Wriddhi Chakraborty ◽  
Wenshen Li ◽  
Suman Datta ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Large Injection

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

2014 ◽  
Vol 778-780 ◽  
pp. 841-844 ◽  
Author(s):  
Koji Nakayama ◽  
Shuji Ogata ◽  
Toshihiko Hayashi ◽  
Tetsuro Hemmi ◽  
Atsushi Tanaka ◽  
...  
Keyword(s):  
High Voltage ◽  
Recovery Time ◽  
Carrier Lifetime ◽  
Low Voltage ◽  
Reduction Rate ◽  
Drift Region ◽  
Pin Diode ◽  
Fully Depleted ◽  
Fast Switching ◽  
Reverse Recovery Time

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.

Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology

2018 ◽  
Vol 86 (7) ◽  
pp. 199-206 ◽  
Author(s):  
Ömür Işıl Aydin ◽  
Judson Robert Holt ◽  
Cyrille Le Royer ◽  
Laks Vanamurthy ◽  
Thomas Feudel ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology
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