High-speed soft-error-immune ECL circuits with fully isolated transistors

1992 ◽  
Vol 39 (3) ◽  
pp. 695-699 ◽  
Author(s):  
K. Ueno
Keyword(s):  
High Speed ◽  
Soft Error

A circuit concept for reducing soft error in high-speed memory cells

10.1109/4.279 ◽  
1988 ◽  
Vol 23 (1) ◽  
pp. 201-203 ◽  
Author(s):  
D.D. Tang ◽  
C.-T. Chuang
Keyword(s):  
High Speed ◽  
Soft Error ◽  
Memory Cells

scholarly journals Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors

2021 ◽  
Author(s):  
Mohammad R.S. Javaheri
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Soft Errors ◽  
Error Rates ◽  
Soft Error ◽  
Delay Faults ◽  
Fault Propagation ◽  
Delay Fault ◽  
Wide Range ◽  
Strength Based

Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

Improvements and Analysis of Neutron Induced Soft Error and Latch-up in High Speed Full CMOS 6T SRAM Products up to 65nm Technology

2004 ◽  
Author(s):  
Soon -Moon Jung ◽  
Hoon Lim ◽  
Wonseok Cho ◽  
Jaehun Jeong ◽  
Youngseop Rah ◽  
...  
Keyword(s):  
High Speed ◽  
Soft Error ◽  
Latch Up

RADIATION EFFECTS IN HIGH SPEED III-V INTEGRATED CIRCUITS

2003 ◽  
Vol 13 (01) ◽  
pp. 277-292 ◽  
Author(s):  
TODD R. WEATHERFORD
Keyword(s):  
Ionizing Radiation ◽  
Integrated Circuits ◽  
Sea Level ◽  
Circuit Design ◽  
Material Properties ◽  
High Speed ◽  
Radiation Effects ◽  
Soft Error ◽  
Device Structures ◽  
Energy Products

The types of applications affected by radiation effects in III-V devices have significantly changed over the last four decades. For most applications III-V ICs have provided sufficient radiation hardness. Some expectations for hardened soft error applications did not materialize until much later. Years of research defined that not only material properties, but device structures, layout practices and circuit design influenced how III-V devices were susceptible to certain radiation effects. The highest performance III-V ICs due to their low power-speed energy products will provide challenges in ionizing radiation environments from sea level to space.

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