Single-wafer integrated semiconductor device processing

1992 ◽  
Vol 39 (1) ◽  
pp. 4-32 ◽  
Author(s):  
M.M. Moslehi ◽  
R.A. Chapman ◽  
M. Wong ◽  
A. Paranjpe ◽  
H.N. Najm ◽  
...  
Keyword(s):  
Semiconductor Device ◽  
Device Processing

Mapping of Process-Induced Dopant Redistributions by Electron Holography

2004 ◽  
Vol 10 (4) ◽  
pp. 462-469 ◽  
Author(s):  
Wolf-Dieter Rau ◽  
Alexander Orchowski
Keyword(s):  
Semiconductor Device ◽  
Device Fabrication ◽  
Electron Holography ◽  
Dopant Diffusion ◽  
Fundamental Parameters ◽  
Device Processing ◽  
Device Structures ◽  
Before And After ◽  
Potential Applications ◽  
Junction Potential

We present and review dopant mapping examples in semiconductor device structures by electron holography and outline their potential applications for experimental investigation of two-dimensional (2D) dopant diffusion on the nanometer scale. We address the technical challenges of the method when applied to transistor structures with respect to quantification of the results in terms of the 2Dp–njunction potential and critically review experimental boundary conditions, accuracy, and potential pitfalls. By obtaining maps of the inner electrostatic potential before and after anneals typically used in device processing, we demonstrate how the “vertical” and “lateral” redistribution of boron during device fabrication can directly be revealed. Such data can be compared with the results of process simulation to extract the fundamental parameters for dopant diffusion in complex device structures.

Photoelectrochemical methods for semiconductor device processing

1993 ◽  
Vol 38 (1) ◽  
pp. 101-106 ◽  
Author(s):  
Paul A. Kohl ◽  
Derek B. Harris
Keyword(s):  
Semiconductor Device ◽  
Device Processing

Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing

2016 ◽  
Vol 2016 (1) ◽  
pp. 000469-000474 ◽  
Author(s):  
Xiao Liu ◽  
Qi Wu ◽  
Dongshun Bai ◽  
Trevor Stanley ◽  
Alvin Lee ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
High Performance ◽  
Large Scale ◽  
Semiconductor Device ◽  
High Vacuum ◽  
Thickness Variation ◽  
Wafer Level ◽  
Device Processing ◽  
Temporary Bonding ◽  
Wafer Processing

Abstract Advanced wafer-level packaging (WLP) techniques, mainly driven by high performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology has been widely studied and developed over the last decade for use in various WLP technologies, such as package-on-package (PoP), fan-out integration, and 2.5-D and 3-D integration using through-silicon-via (TSV). Temporary bonding technology enables handling of thinned substrates (<100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics were developed for temporary wafer bonding applications. These materials target high temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All of these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (TTV < 5 μm) after grinding and have successfully passed a 200°C PECVD process without any delamination during grinding and PECVD processes.

AIGaAs Microelectronic Device Processing Using an as Capping Layer

1993 ◽  
Vol 324 ◽  
Author(s):  
J.K. Grepstad ◽  
H. Husby ◽  
R.W. Bernstein ◽  
B.-O. Fimland
Keyword(s):  
Photoelectron Spectroscopy ◽  
Semiconductor Device ◽  
High Vacuum ◽  
Ultra High Vacuum ◽  
Capping Layer ◽  
Device Processing ◽  
Photoresist Mask ◽  
Novel Method ◽  
A New Technique ◽  
Hydrogen Radicals

AbstractThe case for incorporating an arsenic capping layer in compound semiconductor device processing has been investigated with x-ray photoelectron spectroscopy (XPS), low-energy electron diffraction (LEED) and scanning electron microscopy (SEM). The As cap was found to be stable upon exposure to common processing chemicals, such as acetone, photoresist, developer, and N-methyl-2-pyrrolidone, a common polyimide solvent. A clean, c(4×4)-reconstructed GaAs(001) surface was recovered after thermal desorption of the cap in ultra-high vacuum, for a sample exposed to standard (maskless) photolithography. We also report a new technique for reactive decapping at room temperature, using a beam of hydrogen radicals (H*). Pattern definition in the As cap with ∼ 5 μm linewidth was demonstrated, using this technique. However, XPS and SEM data for the H*-etched specimens showed clear evidence of superficial gallium (sub)oxide and of As residues along the photoresist mask edges. This novel method of As cap patterning thus needs further refinement, before being useful to III-V device processing.

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