Synthesis for testability of highly complex controllers by functional redundancy removal

1999 ◽  
Vol 48 (12) ◽  
pp. 1305-1323 ◽  
Author(s):  
F. Fummi ◽  
D. Sciuto ◽  
M. Serra
VLSI Design ◽  
2002 ◽  
Vol 14 (2) ◽  
pp. 155-169
Author(s):  
Chien-In Henry Chen ◽  
Mahesh Wagh

Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.


2013 ◽  
Vol 224 (1) ◽  
pp. 29-34 ◽  
Author(s):  
Alejandra Perea-Blázquez ◽  
Simon K. Davy ◽  
James J. Bell

Oikos ◽  
1999 ◽  
Vol 84 (2) ◽  
pp. 246 ◽  
Author(s):  
Gary Sullivan ◽  
Joy B. Zedler

Genetics ◽  
2010 ◽  
Vol 186 (4) ◽  
pp. 1285-1293 ◽  
Author(s):  
Kathryn K. Stein ◽  
Jessica E. Nesmith ◽  
Benjamin D. Ross ◽  
Andy Golden

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