Design and analysis of high performance multistage interconnection networks

1997 ◽  
Vol 46 (1) ◽  
pp. 110-117 ◽  
Author(s):  
S.K. Bhogavilli ◽  
H. Abu-Amara
Keyword(s):  
Interconnection Networks ◽  
High Performance ◽  
Multistage Interconnection Networks

A Survey of Multistage Interconnection Networks

2020 ◽  
Vol 13 (2) ◽  
pp. 165-183
Author(s):  
Amit Prakash ◽  
Dilip K. Yadav ◽  
Arvind Choubey
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
High Performance ◽  
Fault Tolerant ◽  
Network Architectures ◽  
Multistage Interconnection Networks ◽  
Processing Elements ◽  
Multiprocessor Architectures ◽  
Network Functionality

Background: Multistage interconnection networks are being used in computer and communications. Multiprocessor architectures for parallel computing exercise these interconnection networks for connecting various processing elements and transfer data between sub-systems of a digital system. The vast diversity of the field poses an obstacle to realize different kinds of interconnection networks and their relationship. Methods: This paper consists of an extensive survey of multistage interconnection networks. Results: A broad classification of multistage interconnection networks based on network functionality, reliability and fault tolerance is presented in order to emphasize the important principles which differentiate the network architectures. For each class of network, significant results are given and the basic design principles are explained. Conclusion: The various multistage interconnection networks design provide high performance, availability, throughput, lower latency, less power consumption along with improved fault-tolerance and reliability. However, there is a rising demand for new fault-tolerant and reliable multistage interconnection networks.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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