Augmented binary hypercube: a new architecture for processor management

1996 ◽  
Vol 45 (8) ◽  
pp. 980-984 ◽  
Author(s):  
H. Lalgudi ◽  
L.F. Akyildiz ◽  
S. Yalamanchili
Keyword(s):  
Processor Management

Evaluation Scheme for NoC-based CMP with Integrated Processor Management System

2010 ◽  
Vol 56 (2) ◽  
pp. 157-168 ◽  
Author(s):  
Dawid Zydek ◽  
Henry Selvaraj ◽  
Leszek Koszałka ◽  
Iwona Poźniak-Koszałka
Keyword(s):  
Load Balance ◽  
Management System ◽  
Evaluation System ◽  
Chip Multiprocessors ◽  
Limiting Factor ◽  
Full Potential ◽  
Evaluation Scheme ◽  
Traffic Characteristic ◽  
Processor Management ◽  
On Chip

Evaluation Scheme for NoC-based CMP with Integrated Processor Management SystemWith the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.

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