Adaptation of the Mactaggart and Jack complex multiplication algorithm for floating-point operators

1992 ◽  
Vol 41 (10) ◽  
pp. 1324-1326
Author(s):  
R.J. Cosentino ◽  
J.J. Vaccaro
Keyword(s):  
Complex Multiplication ◽  
Floating Point ◽  
Multiplication Algorithm

scholarly journals Implementation of 64 Bit Complex Floating-Point Multiplier on FPGA using Vedic Mathematics Sutra- Urdhva Tiryagbhyam

2020 ◽  
Vol 9 (4) ◽  
pp. 2986-2989
Keyword(s):  
System Performance ◽  
Communication Systems ◽  
Complex Multiplication ◽  
Digital Signal ◽  
Floating Point ◽  
Verilog Hdl ◽  
Low Area ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Ripple Carry Adder

Multipliers play crucial role in present days in the area of digital signal processing and in communication systems applications. The entire system performance depends on speed area and power of the multipliers. In our paper, we developed a 64x64 bit complex floating-point multiplier with 64bit IEEE 754 format multipliers having less delay. Vedic multiplier of ripple carry adder based is suggested for mantissa multiplication in IEEE 754 format. Suggested Vedic multiplier uses historic Vedic Indian mathematics sutra called UrdhvaTiryagbhyam for Vedic multiplication. The architecture Proposed for 64x64 bit complex floating-point multiplier is in Xilinx ISE 14.2 FPGA navigator in Verilog HDL. Eventually, the outcomes of the suggested multiplier will differentiate with traditional booth multiplier and array multiplier which represents clearly that complex multiplication using suggested architecture gives less delay, power and low area.

scholarly journals Floating Point Multiplication Based on Schonhage Strassen Algorithm

2018 ◽  
Vol 7 (2.20) ◽  
pp. 14
Author(s):  
B Srikanth ◽  
M Siva Kumar ◽  
K Hari Kishore
Keyword(s):  
Fixed Point ◽  
Real Time ◽  
Floating Point ◽  
Single Precision ◽  
Point Multiplication ◽  
Multiplication Algorithm ◽  
Integer Multiplication

In this paper, the single precision float point multiplication is performed using the Schonhage Strassen Algorithm. There are several types of floating point multiplications like Karatsubha and Toom cook. The Schonhage Strassen algorithm is conventionally a fixed point integer multiplication algorithm. The main advantage of the Schonhage Strassen multiplication is that, the multiplication of integer values greater than 5 digits ranging from 2215 to 2217 bit values proves to be efficient. The validation of the proposed floating point multiplication is done using FPGA real time implementation. The analysis of parameters like area and power are evaluated.  

A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

2013 ◽  
Vol 811 ◽  
pp. 441-446
Author(s):  
Jun Ding ◽  
Na Li
Keyword(s):  
Fourier Transform ◽  
High Speed ◽  
Complex Multiplication ◽  
Floating Point ◽  
System Throughput ◽  
Cordic Algorithm ◽  
Clock Frequency ◽  
Sample Number ◽  
Fft Processor ◽  
Dual Core

This paper presents a dual-core floating point FFT processor design based on CORDIC algorithm, enabling high-speed floating-point real-time FFT computation, and its time complexity is (N / 4) Log (N / 2). The design unifiesthe floating complex multiplication and the evaluationof twiddle factors into an iteration, which not only reduces the complexity of complex multiplication but also reduces the difficulty when the butterfly unit deals with floating-point in fast Fourier transform. The butterfly unit unaffected by the size of external memory can handle the Fourier transform with high sample number, both having wider handling range and high handling precision. It uses two logical cores and pipeline technology to improve overall system throughput, with simple hardware structure and system stability.At the end, it does the post-simulation on the Altera chip EP2C35F672C6, and its timing simulation can be run properly under the 50 MHz clock frequency.

scholarly journals EFFICIENT FLOATING POINT FAST FOURIER TRANSFORM BUTTERFLY ARCHITECTURE USING BINARY SIGNED DIGIT MULTIPLIER AND ADDERS

2017 ◽  
Vol 10 (13) ◽  
pp. 73
Author(s):  
Shivani Acharya ◽  
Augusta Sophy Beulet
Keyword(s):  
Signal Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Time Domain ◽  
Complex Multiplication ◽  
Digital Signal ◽  
Floating Point ◽  
Addition And Subtraction ◽  
The One ◽  
Point Fast Fourier Transform

Fast Fourier transform (FFT) is one of the most important tools in digital signal processing as well as communication system because transforming time domain to S-plane is very convenient using FFT. As FFT uses various techniques to convert a signal from time domain to S-domain and inverse, out of which butterfly technique is the one on which paper is focused on. Butterfly technique uses additions and multiplications of operands to get the required output. Floating point (FP) is used as operands due to their flexibility. As the computations involving FP has less speed, we have used binary signed digit (BSD). BSD will take the less time for addition and subtraction. Three bit BSD adder and FP adder together will make a fused dot product add (FDPA) unit. In FDPA, unit addition and subtraction will be one group and multiplication will be one group and then their respective results will be fused. Modified booth encoding and decoding algorithm are used here to make the complex multiplication with ease. 

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