Enhanced analog "yields" cost-effective systems-on-chip

1999 ◽  
Vol 15 (2) ◽  
pp. 12-22 ◽  
Author(s):  
T.B. Tarim ◽  
M. Ismail
Keyword(s):  
Cost Effective ◽  
Systems On Chip ◽  
On Chip

scholarly journals 0.16 µm–BCD Silicon Photomultipliers with Sharp Timing Response and Reduced Correlated Noise

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3763 ◽  
Author(s):  
Mirko Sanzaro ◽  
Fabio Signorelli ◽  
Paolo Gattari ◽  
Alberto Tosi ◽  
Franco Zappa
Keyword(s):  
Detection Efficiency ◽  
Cost Effective ◽  
Digital Processing ◽  
Correlated Noise ◽  
Silicon Photomultipliers ◽  
Photon Detection ◽  
Systems On Chip ◽  
Photon Detection Efficiency ◽  
On Chip

Silicon photomultipliers (SiPMs) have improved significantly over the last years and now are widely employed in many different applications. However, the custom fabrication technologies exploited for commercial SiPMs do not allow the integration of any additional electronics, e.g., on-chip readout and analog (or digital) processing circuitry. In this paper, we present the design and characterization of two microelectronics-compatible SiPMs fabricated in a 0.16 µm–BCD (Bipolar-CMOS-DMOS) technology, with 0.67 mm × 0.67 mm total area, 10 × 10 square pixels and 53% fill-factor (FF). The photon detection efficiency (PDE) surpasses 33% (FF included), with a dark-count rate (DCR) of 330 kcps. Although DCR density is worse than that of state-of-the-art SiPMs, the proposed fabrication technology enables the development of cost-effective systems-on-chip (SoC) based on SiPM detectors. Furthermore, correlated noise components, i.e., afterpulsing and optical crosstalk, and photon timing response are comparable to those of best-in-class commercial SiPMs.

AN ANALYTICAL COMPARISON OF THE SPIDERGON AND RECTANGULAR MESH NoCs

2009 ◽  
Vol 10 (01n02) ◽  
pp. 167-188
Author(s):  
MAHMOUD MOADELI ◽  
ALI SHAHRABI ◽  
WIM VANDERBAUWHEDE ◽  
MOHAMED OULD-KHAOUA
Keyword(s):  
Discrete Event ◽  
Cost Effective ◽  
Network Throughput ◽  
Analytical Models ◽  
Networks On Chip ◽  
Mesh Topology ◽  
Systems On Chip ◽  
Rectangular Mesh ◽  
On Chip ◽  
Scalable Communication

Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.

scholarly journals On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Jian Lu ◽  
Hongwei Jia ◽  
Andres Arias ◽  
Xun Gong ◽  
Z. John Shen
Keyword(s):  
Power Systems ◽  
High Efficiency ◽  
State Of The Art ◽  
Cost Effective ◽  
Magnetic Components ◽  
Systems On Chip ◽  
Cost Effective Approach ◽  
Coupling Factors ◽  
On Chip ◽  
Novel Concept

A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC). We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.

Effective Memory Architectures of Multi-Processor Systems-on-Chip

2010 ◽  
Vol 3 (3) ◽  
pp. 218-231
Author(s):  
Ni Zhou ◽  
Fei Qiao ◽  
Huazhong Yang ◽  
Hui Wang
Keyword(s):  
Systems On Chip ◽  
On Chip ◽  
Memory Architectures

МЕТОДЫ ДОСТИЖЕНИЯ МАКСИМАЛЬНОЙ ЭФФЕКТИВНОСТИ ПЛАТФОРМЫ ПРОТОТИПИРОВАНИЯ ВЫСОКОПРОИЗВОДИТЕЛЬНЫХ СИСТЕМ НА КРИСТАЛЛЕ НА ЗАДАЧАХ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА

2020 ◽  
Vol 96 (3s) ◽  
pp. 585-588
Author(s):  
С.Е. Фролова ◽  
Е.С. Янакова
Keyword(s):  
Neural Network ◽  
Artificial Intelligence ◽  
Computer Vision ◽  
High Performance ◽  
Systems On Chip ◽  
High Performance Systems ◽  
On Chip ◽  
Network Technologies ◽  
Neural Network Technologies

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

scholarly journals 3D printed microfluidic lab-on-a-chip device for fiber-based dual beam optical manipulation

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Haoran Wang ◽  
Anton Enders ◽  
John-Alexander Preuss ◽  
Janina Bahnemann ◽  
Alexander Heisterkamp ◽  
...  
Keyword(s):  
Optical Fibers ◽  
Single Cells ◽  
Lab On A Chip ◽  
Cost Effective ◽  
Optical Manipulation ◽  
Hydrodynamic Focusing ◽  
Trapping Region ◽  
Dual Beam ◽  
3D Printed ◽  
On Chip

Abstract3D printing of microfluidic lab-on-a-chip devices enables rapid prototyping of robust and complex structures. In this work, we designed and fabricated a 3D printed lab-on-a-chip device for fiber-based dual beam optical manipulation. The final 3D printed chip offers three key features, such as (1) an optimized fiber channel design for precise alignment of optical fibers, (2) an optically clear window to visualize the trapping region, and (3) a sample channel which facilitates hydrodynamic focusing of samples. A square zig–zag structure incorporated in the sample channel increases the number of particles at the trapping site and focuses the cells and particles during experiments when operating the chip at low Reynolds number. To evaluate the performance of the device for optical manipulation, we implemented on-chip, fiber-based optical trapping of different-sized microscopic particles and performed trap stiffness measurements. In addition, optical stretching of MCF-7 cells was successfully accomplished for the purpose of studying the effects of a cytochalasin metabolite, pyrichalasin H, on cell elasticity. We observed distinct changes in the deformability of single cells treated with pyrichalasin H compared to untreated cells. These results demonstrate that 3D printed microfluidic lab-on-a-chip devices offer a cost-effective and customizable platform for applications in optical manipulation.

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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