Ion-channeling determination of the atomic-site location of antimony at the (111) silicon–silicon dioxide interface

1987 ◽  
Vol 36 (12) ◽  
pp. 6532-6538 ◽  
Author(s):  
A. D. F. Kahn ◽  
J. A. Eades
Keyword(s):  
Silicon Dioxide ◽  
Site Location ◽  
Atomic Site ◽  
Ion Channeling ◽  
Silicon Silicon ◽  
Silicon Silicon Dioxide Interface

Dopant Site Location by Electron Channeling in Ion Implanted Silicon

1983 ◽  
Vol 31 ◽  
Author(s):  
S. J. Pennycook ◽  
J. Narayan ◽  
O.W. Holland
Keyword(s):  
Electron Microscope ◽  
Electron Micrographs ◽  
Site Location ◽  
Electron Channeling ◽  
Ion Channeling ◽  
Stages Of Growth ◽  
Early Stages ◽  
Simple Ratio ◽  
Implantation Profile

ABSTRACTA simple ratio technique using the phenomenon of electron channeling can be used to measure the substitutional concentrations of dopants in semiconductors on a submicron scale.A comparison was made between electron and ion channeling measurements on Si-Sb alloy samples having a range of nonsubstitutional fractions of Sb.Good agreement was obtained but both measurements indicated considerably more nonsubstitutional dopant than could be accounted for by precipitates observed in electron micrographs. The discrepancy can be explained if the precipitates are coherent in the early stages of growth and have their planes located interstitially with respect to the Si planes. The sensitivity of the electron channeling measurements to the implantation profile was investigated and found to be small.The determination of local dopant profiles in the electron microscope is described.

Gate Quality Oxides Prepared by Rapid Thermal Chemical Vapor Deposition

1993 ◽  
Vol 334 ◽  
Author(s):  
R.T. Kuehn ◽  
X. Xu ◽  
D.J. Holcombe ◽  
V. Misra ◽  
J.J. Wortman ◽  
...  
Keyword(s):  
Nitrous Oxide ◽  
Silicon Dioxide ◽  
Flow Rate ◽  
Rate Ratio ◽  
Surface Cleaning ◽  
Flow Rate Ratio ◽  
Deposition Rates ◽  
Gate Oxides ◽  
Silicon Silicon ◽  
Silicon Silicon Dioxide Interface

AbstractAs the feature size of MOSFET devices shrink, issues such as thermal budget associated with controlling channel doping profiles and oxide growth kinetics raise concerns about using thermally grown furnace oxides for deep-submicron device applications. To address these concerns, we have developed a new RTCVD oxide process using a gas system of silane and nitrous oxide. The RTCVD oxides are deposited in a lamp-heated, cold wall, RTP system. Deposition rates ranging from 55 Å/min. to 624 Å/min. can be achieved at 800°C with silane nitrous oxide flow rate ratio of 2% and total pressure ranging from 3 to 10 Torr. The results indicate that this RTCVD process can be used to deposit both thin gate and thick isolation insulators for single wafer processing. Deposition rates of the RTCVD oxides exhibit a nonlinear dependence on the total deposition pressure. Electrical characterization of the as-deposited RTCVD oxides shows a mid-gap interface trap density of < 5×1010 eV−1 cm−2 and an average breakdown field of 13MV/cm. AES, RBS and TEM analyses have been used to study surface cleaning effects on the silicon-silicon dioxide interface quality and to determine the chemical composition of the RTCVD oxides. The results show that RTCVD oxides with stoichiometric composition and atomic flat silicon-silicon dioxide interface can be achieved using silane nitrous oxide flow rate ratio of <2%. I-V characteristics and transconductance degradation under hot carrier stress for MOSFET's using as-deposited RTCVD gate oxides have been found to be comparable to those of MOSFET's using thermal gate oxides.

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