scholarly journals Spatially-explicit modeling improves empirical characterization of dispersal: theory and a case study

2019 ◽  
Author(s):  
Petteri Karisto ◽  
Frédéric Suffert ◽  
Alexey Mikaberidze
Keyword(s):  
Empirical Studies ◽  
Dispersal Kernel ◽  
Spatially Explicit ◽  
Zymoseptoria Tritici ◽  
Rain Splash ◽  
Spatially Explicit Modeling ◽  
Dispersal Kernels ◽  
Source Geometry

AbstractDispersal is a key ecological process. An individual dispersal event has a source and a destination, both are well localized in space and can be seen as points. A probability to move from a source point to a destination point can be described by a dispersal kernel. However, when we measure dispersal, the source of dispersing individuals is usually an area, which distorts the shape of the dispersal gradient compared to the dispersal kernel. Here, we show theoretically how different source geometries affect the gradient shape depending on the type of the kernel. We present an approach for estimating dispersal kernels from measurements of dispersal gradients independently of the source geometry. Further, we use the approach to achieve the first field measurement of dispersal kernel of an important fungal pathogen of wheat, Zymoseptoria tritici. Rain-splash dispersed asexual spores of the pathogen spread on a scale of one meter. Our results demonstrate how analysis of dispersal data can be improved to achieve more rigorous measures of dispersal. Our findings enable a direct comparison between outcomes of different experiments, which will allow to acquire more knowledge from a large number of previous empirical studies of dispersal.

Construction of plastic contact deformation maps on ceramics: a case study on aluminum nitride

1996 ◽  
Vol 54 ◽  
pp. 636-637
Author(s):  
D. L. Callahan
Keyword(s):  
Plastic Deformation ◽  
Aluminum Nitride ◽  
Mechanical Response ◽  
Three Dimensional ◽  
Bright Field Image ◽  
Perfectly Plastic ◽  
Contrast Analysis ◽  
Deformation Patterns

Modern polishing, precision machining and microindentation techniques allow the processing and mechanical characterization of ceramics at nanometric scales and within entirely plastic deformation regimes. The mechanical response of most ceramics to such highly constrained contact is not predictable from macroscopic properties and the microstructural deformation patterns have proven difficult to characterize by the application of any individual technique. In this study, TEM techniques of contrast analysis and CBED are combined with stereographic analysis to construct a three-dimensional microstructure deformation map of the surface of a perfectly plastic microindentation on macroscopically brittle aluminum nitride.The bright field image in Figure 1 shows a lg Vickers microindentation contained within a single AlN grain far from any boundaries. High densities of dislocations are evident, particularly near facet edges but are not individually resolvable. The prominent bend contours also indicate the severity of plastic deformation. Figure 2 is a selected area diffraction pattern covering the entire indentation area.

Integrating The Geophysical Characterization Of Seismic Thin Beds With Stochastic Reservoir Modeling: A Case Study From The Kutei Basin (Offshore Kalimantan, Indonesia)

2011 ◽  
Author(s):  
Giorgio Rocco Cavanna ◽  
Ernesto Caselgrandi ◽  
Elisa Corti ◽  
Alessandro Amato del Monte ◽  
Massimo Fervari ◽  
...  
Keyword(s):  
Reservoir Modeling ◽  
Geophysical Characterization

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

2007 ◽  
Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel
Keyword(s):  
Failure Mode ◽  
Failure Modes ◽  
Fault Modeling ◽  
Mode Analysis ◽  
Root Cause ◽  
Failure Mode Analysis

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

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