scholarly journals CMU Array: A 3D Nano-Printed, Customizable Ultra-High-Density Microelectrode Array Platform

2019 ◽  
Author(s):  
Mohammad Sadeq Saleh ◽  
Sandra M. Ritchie ◽  
Mark A. Nicholas ◽  
Rriddhiman Bezbaruah ◽  
Jay W. Reddy ◽  
...  
Keyword(s):  
Large Scale ◽  
Microelectrode Array ◽  
Printed Circuit Boards ◽  
Biological Tissues ◽  
Circuit Boards ◽  
Clinical Neuroscience ◽  
Printed Circuit ◽  
Computer Interfaces ◽  
3D Printed ◽  
Technological Limitations

AbstractMicroelectrode arrays (MEAs) provide the means to record electrophysiological activity fundamental to both basic and clinical neuroscience (e.g. brain-computer interfaces). Despite recent advances, current MEAs have significant limitations – including low recording density, fragility, expense, and the inability to optimize the probe to individualized study or patient needs. Here we address the technological limitations through the utilization of the newest developments in 3D nanoparticle printing.1 Our ‘CMU Arrays’ possess previously impossible electrode densities (> 6000 channels/cm2) with tip diameters as small as 10 μm. Most importantly, the probes are entirely customizable owing to the adaptive manufacturing process. Any combination of individual shank lengths, impedances, and layouts are possible. This is achieved in part via our new multi-layer, multi material, custom 3D-printed circuit boards, a fabrication advancement in itself. This device design enables new experimental avenues of targeted, large-scale recording of electrical signals from a variety of biological tissues.

Excimer Laser Drill for Multilayer Printed Circuit Boards: From Advanced Development to Factory Floor

MRS Bulletin ◽  
1989 ◽  
Vol 14 (12) ◽  
pp. 49-53 ◽  
Author(s):  
Friedrich Bachmann
Keyword(s):  
Excimer Laser ◽  
High Speed ◽  
Large Scale ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Multichip Module ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Delay Times

A novel excimer laser process has been developed for generating cylindrical via holes with an aspect ratio of about one. The fabrication process is being successfully run on a production line for a highly miniaturized printed circuit board used for the multichip module in the new Siemens 7500 H 90 mainframe computer. The process is outstanding in terms of reliability and reproducibility. To the best of our knowledge, this is the first that that excimer lasers have been put into large-scale use in an industrial environment.Since signal delay times for chips have decreased much more rapidly than delay times for packaging, the computing speed of high-speed computers is restricted by the packaging techniques used. Therefore, further development of packaging technology became a prime objective for those developing high-performance computers. Packaging delay times had to be reduced drastically to keep up with increasingly shorter chip delay times. This, in effect, meant that a greater packaging density had to be implemented.A novel planar packaging technique has lead to considerable progress in solving this problem. This technique has been described in detail elsewhere. A key component in this technology is a multichip module, which can take in each of 16 areas, either an LSI module with 320 leads or 9 MSI modules with 52 leads as “bare” ICs. This means that a micro-wiring printed circuit board of this kind can accomodate between 16 (LSI) and 144 (MSI) chips. This article describes how these printed circuit boards are manufactured.As the specifications (Table I) show, blind vias 80 μm in diameter at a pitch of 0.5 mm have to be made in a 16-layer printed circuit board. It is intended that these blind vias will provide the through-contact for neighboring layers. The excimer laser plays a major role in this process.

Evaluating waste printed circuit boards recycling: Opportunities and challenges, a mini review

2017 ◽  
Vol 35 (4) ◽  
pp. 346-356 ◽  
Author(s):  
Abhishek Kumar Awasthi ◽  
Gabriel Ionut Zlamparet ◽  
Xianlai Zeng ◽  
Jinhui Li
Keyword(s):  
Large Scale ◽  
Printed Circuit Boards ◽  
Review Article ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Waste Printed Circuit Boards ◽  
Valuable Metals ◽  
Rapid Generation

Rapid generation of waste printed circuit boards has become a very serious issue worldwide. Numerous techniques have been developed in the last decade to resolve the pollution from waste printed circuit boards, and also recover valuable metals from the waste printed circuit boards stream on a large-scale. However, these techniques have their own certain specific drawbacks that need to be rectified properly. In this review article, these recycling technologies are evaluated based on a strength, weaknesses, opportunities and threats analysis. Furthermore, it is warranted that, the substantial research is required to improve the current technologies for waste printed circuit boards recycling in the outlook of large-scale applications.

A Study on Impact Stresses in Ceramic Capacitors

2013 ◽  
Author(s):  
Takashi Kawakami ◽  
Noriyo Horikawa ◽  
Takahiro Kinoshita ◽  
Tomohiro Inagaki
Keyword(s):  
Large Scale ◽  
Printed Circuit Boards ◽  
Mechanical Design ◽  
Circuit Boards ◽  
Multilayer Ceramic Capacitors ◽  
Printed Circuit ◽  
Ceramic Capacitors ◽  
Pcb Manufacturing ◽  
Split Hopkinson ◽  
Computing Method

Multilayer ceramic capacitors (MLCCs) are used very widely as electric devices on printed circuit boards (PCBs). Impact loads are applied on MLCCs during PCB manufacturing processes with fast mounting machines or floor dropping of mobile appliances and MLCCs may crack sometime due to the mechanical design. In this paper, impact stresses, which were induced in MLCCs by split Hopkinson bar impact tests, were analyzed with large scale parallel computing method.

THREE-DIMENSIONAL PACKAGING FOR HIGH-PERFORMANCE INTERCONNECT IN LARGE-SCALE VLSI SYSTEMS

1995 ◽  
Vol 06 (04) ◽  
pp. 613-630
Author(s):  
ANDRÉ DEHON ◽  
FRED DRENCKHAHN ◽  
THOMAS KNIGHT ◽  
HENRY MINSKY
Keyword(s):  
Transit Time ◽  
High Performance ◽  
Large Scale ◽  
Printed Circuit Boards ◽  
Large Range ◽  
Three Dimensional ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Vlsi System ◽  
Spatial Dimensions

The transit time through the interconnect between VLSI components can be a significant fraction of the latency in a large VLSI system. In this paper we describe a scheme for dense, three-dimensional packaging of VLSI components which reduces chip-to-chip transit latencies by reducing interconnect distances. Our packaging scheme sandwiches layers of conventional printed-circuit boards between layers of packaged components to efficiently utilize all three spatial dimensions for interconnect. We introduce the key components of our stack packaging scheme and show how they combine to provide efficient housing for a large range of large-scale VLSI systems.

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