Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid

2010 ◽  
Vol 368 (1925) ◽  
pp. 3967-3981 ◽  
Author(s):  
James Alfred Walker ◽  
Richard Sinnott ◽  
Gordon Stewart ◽  
James A. Hilder ◽  
Andy M. Tyrrell
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Circuit Simulation ◽  
Fitness Function ◽  
Three Dimensional ◽  
Simulation Models ◽  
Oxide Semiconductor ◽  
Standard Cell ◽  
The Impact

The project Meeting the Design Challenges of nano-CMOS Electronics ( http://www.nanocmos.ac.uk ) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Studying the Impact of Return Current Path on the EM Simulation of High-speed Package Designs

2011 ◽  
Vol 2011 (1) ◽  
pp. 000061-000068
Author(s):  
Darryl Kostka ◽  
Antonio Ciccomancini Scogna
Keyword(s):  
High Speed ◽  
Ground Plane ◽  
Three Dimensional ◽  
Simulation Models ◽  
Current Path ◽  
Cavity Resonances ◽  
Simulation Results ◽  
The Impact ◽  
Simulation Time

Three-dimensional electromagnetic simulation models are often simplified in order to reduce the simulation time and memory requirements without sacrificing the accuracy of the results. A commonly adopted methodology in the simulation of electronic package designs is to truncate the size of the package model leaving only a few important features surrounding the nets of interest. In this paper we demonstrate that this simplification can have a significant impact of the simulation results if it is not performed carefully and it can introduce spurious/non physical resonances. The interaction between cavities and signals is first studied using a simple coupled differential via test structure. It is demonstrated that the return currents generated by these vias excite cavity resonances in power-ground plane pairs causing them to behave as parallel-plate waveguides. The role of interplane shorting vias in suppressing cavity resonances is then investigated and the impact of boundary conditions on the simulation results of package models is also shown and discussed. Finally, a realistic complex multilayer package model is analyzed and it is demonstrate that through proper truncation of the geometry, accurate results can be obtained.

A Novel Low Power Technique for FinFET Domino OR Logic

2020 ◽  
pp. 2150117
Author(s):  
Kajal ◽  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Logic Gates ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Large Power ◽  
Leakage Reduction ◽  
The Impact

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

Studying the Impact of Return Current Path on the EM Simulation of High-Speed Package and Board Designs

2012 ◽  
Vol 9 (2) ◽  
pp. 52-64
Author(s):  
Darryl Kostka ◽  
Antonio Ciccomancini Scogna
Keyword(s):  
High Speed ◽  
Ground Plane ◽  
Three Dimensional ◽  
Simulation Models ◽  
Combined Model ◽  
Current Path ◽  
Cavity Resonances ◽  
Simulation Results ◽  
The Impact

Three-dimensional electromagnetic simulation models are often simplified in order to reduce simulation time and memory requirements without sacrificing the accuracy of the results. A commonly adopted methodology in the simulation of complex electronic package and board designs is to truncate the size of the model, leaving only a few important features surrounding the nets of interest. In this paper we demonstrate that this simplification can have a significant impact on the simulation results if it is not performed carefully, and it can introduce spurious nonphysical resonances. The interaction between cavities and signals is first studied using a simple coupled differential via test structure. It is demonstrated that the return currents generated by these vias excite cavity resonances in power-ground plane pairs causing them to behave as parallel-plate waveguides. The role of interplane shorting vias in suppressing cavity resonances is then investigated and the impact of boundary conditions on the simulation results of package models is also shown and discussed. The focus is then shifted to PCB/package cosimulation and the impact of different truncation schemes is discussed through the simulation of test structures of varying complexity. A simulation methodology is then proposed and is verified for a combined model of a realistic complex multilayer package and board and it is demonstrated that accurate results can be obtained through proper truncation of the geometry.

scholarly journals Prevention of Mountain Disasters and Maintenance of Residential Area through Real-Time Terrain Rendering

2021 ◽  
Vol 13 (5) ◽  
pp. 2950
Author(s):  
Su-Kyung Sung ◽  
Eun-Seok Lee ◽  
Byeong-Seok Shin
Keyword(s):  
Real Time ◽  
Graphics Processing Units ◽  
High Speed ◽  
Large Scale ◽  
Civil Engineering ◽  
Three Dimensional ◽  
Sampled Data ◽  
Residential Areas ◽  
Terrain Rendering ◽  
Mountain Disasters

Climate change increases the frequency of localized heavy rains and typhoons. As a result, mountain disasters, such as landslides and earthworks, continue to occur, causing damage to roads and residential areas downstream. Moreover, large-scale civil engineering works, including dam construction, cause rapid changes in the terrain, which harm the stability of residential areas. Disasters, such as landslides and earthenware, occur extensively, and there are limitations in the field of investigation; thus, there are many studies being conducted to model terrain geometrically and to observe changes in terrain according to external factors. However, conventional topography methods are expressed in a way that can only be interpreted by people with specialized knowledge. Therefore, there is a lack of consideration for three-dimensional visualization that helps non-experts understand. We need a way to express changes in terrain in real time and to make it intuitive for non-experts to understand. In conventional height-based terrain modeling and simulation, there is a problem in which some of the sampled data are irregularly distorted and do not show the exact terrain shape. The proposed method utilizes a hierarchical vertex cohesion map to correct inaccurately modeled terrain caused by uniform height sampling, and to compensate for geometric errors using Hausdorff distances, while not considering only the elevation difference of the terrain. The mesh reconstruction, which triangulates the three-vertex placed at each location and makes it the smallest unit of 3D model data, can be done at high speed on graphics processing units (GPUs). Our experiments confirm that it is possible to express changes in terrain accurately and quickly compared with existing methods. These functions can improve the sustainability of residential spaces by predicting the damage caused by mountainous disasters or civil engineering works around the city and make it easy for non-experts to understand.

scholarly journals 3DIV update for 2021: a comprehensive resource of 3D genome and 3D cancer genome

2020 ◽  
Vol 49 (D1) ◽  
pp. D38-D46
Author(s):  
Kyukwang Kim ◽  
Insu Jang ◽  
Mooyoung Kim ◽  
Jinhyuk Choi ◽  
Min-Seo Kim ◽  
...  
Keyword(s):  
Cell Line ◽  
Large Scale ◽  
Three Dimensional ◽  
Cancer Cell Line ◽  
Cancer Genome ◽  
Structural Variations ◽  
3D Genome ◽  
Tightly Coupled ◽  
Regulatory Effects ◽  
The Impact

Abstract Three-dimensional (3D) genome organization is tightly coupled with gene regulation in various biological processes and diseases. In cancer, various types of large-scale genomic rearrangements can disrupt the 3D genome, leading to oncogenic gene expression. However, unraveling the pathogenicity of the 3D cancer genome remains a challenge since closer examinations have been greatly limited due to the lack of appropriate tools specialized for disorganized higher-order chromatin structure. Here, we updated a 3D-genome Interaction Viewer and database named 3DIV by uniformly processing ∼230 billion raw Hi-C reads to expand our contents to the 3D cancer genome. The updates of 3DIV are listed as follows: (i) the collection of 401 samples including 220 cancer cell line/tumor Hi-C data, 153 normal cell line/tissue Hi-C data, and 28 promoter capture Hi-C data, (ii) the live interactive manipulation of the 3D cancer genome to simulate the impact of structural variations and (iii) the reconstruction of Hi-C contact maps by user-defined chromosome order to investigate the 3D genome of the complex genomic rearrangement. In summary, the updated 3DIV will be the most comprehensive resource to explore the gene regulatory effects of both the normal and cancer 3D genome. ‘3DIV’ is freely available at http://3div.kr.

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

scholarly journals Catalytic production of impurity-free V3.5+ electrolyte for vanadium redox flow batteries

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Jiyun Heo ◽  
Jae-Yun Han ◽  
Soohyun Kim ◽  
Seongmin Yuk ◽  
Chanyong Choi ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Catalytic Reduction ◽  
Continuous Production ◽  
Vanadium Redox Flow Battery ◽  
Manufacturing Cost ◽  
Chemical Production ◽  
High Manufacturing Cost ◽  
Vanadium Redox

Abstract The vanadium redox flow battery is considered one of the most promising candidates for use in large-scale energy storage systems. However, its commercialization has been hindered due to the high manufacturing cost of the vanadium electrolyte, which is currently prepared using a costly electrolysis method with limited productivity. In this work, we present a simpler method for chemical production of impurity-free V3.5+ electrolyte by utilizing formic acid as a reducing agent and Pt/C as a catalyst. With the catalytic reduction of V4+ electrolyte, a high quality V3.5+ electrolyte was successfully produced and excellent cell performance was achieved. Based on the result, a prototype catalytic reactor employing Pt/C-decorated carbon felt was designed, and high-speed, continuous production of V3.5+ electrolyte in this manner was demonstrated with the reactor. This invention offers a simple but practical strategy to reduce the production cost of V3.5+ electrolyte while retaining quality that is adequate for high-performance operations.

FPGA-Based Intelligent Software Hardening Chip for Computer Numerical Control System

2011 ◽  
Vol 105-107 ◽  
pp. 2217-2220
Author(s):  
Mu Lan Wang ◽  
Jian Min Zuo ◽  
Kun Liu ◽  
Xing Hua Zhu
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Position Control ◽  
Computer Numerical Control ◽  
Numerical Control ◽  
Cnc Machine Tools ◽  
Cnc Machine ◽  
Cnc System ◽  
Intelligent Software

In order to meet the development demands for high-speed and high-precision of Computer Numerical Control (CNC) machine tools, the equipped CNC systems begin to employ the technical route of software hardening. Making full use of the advanced performance of Large Scale Integrated Circuits (LSIC), this paper puts forward using Field Programmable Gates Array (FPGA) for the functional modules of CNC system, which is called Intelligent Software Hardening Chip (ISHC). The CNC system architecture with high performance is constructed based on the open system thought and ISHCs. The corresponding programs can be designed with Very high speed integrate circuit Hardware Description Language (VHDL) and downloaded into the FPGA. These hardening modules, including the arithmetic module, contour interpolation module, position control module and so on, demonstrate that the proposed schemes are reasonable and feasibility.

Age-Related Differences in Throwing Techniques Used by the Catcher in Baseball

1994 ◽  
Vol 6 (3) ◽  
pp. 225-235 ◽  
Author(s):  
Shinji Sakurai ◽  
Bruce Elliott ◽  
J. Robert Grove
Keyword(s):  
High Speed ◽  
High Performance ◽  
Age Groups ◽  
Three Dimensional ◽  
Transformation Method ◽  
High Speed Photography ◽  
Two Phase ◽  
Ball Speed ◽  
Age Related ◽  
Release Speed

Three-dimensional (3-D) high speed photography was used to record the overarm throwing actions of five open-age, four 18-year-old, six 16-year- old, and six 14-year-old high-performance baseball catchers. The direct linear transformation method was used for 3-D space reconstruction from 2-D images of the catchers throwing from home plate to second base recorded using two phase-locked cameras operating at a nominal rate of 200 Hz. Selected physical capacity measures were also recorded and correlated with ball release speed. In general, anthropometric and strength measures significantly increased through the 14-year-old to open-age classifications, while a range of correlation coefficients from .50 to .84 was recorded between these physical capacities and ball speed at release. While many aspects of the kinematic data at release were similar, the key factors of release angle and release speed varied for the different age groups.

Sign in / Sign up

Export Citation Format

Share Document