Power Optimization in Logic Synthesis for Mixed Polarity Reed-Muller Logic Circuits

2014 ◽  
Vol 58 (6) ◽  
pp. 1306-1313 ◽  
Author(s):  
X. Wang ◽  
Y. Lu ◽  
Y. Zhang ◽  
Z. Zhao ◽  
T. Xia ◽  
...  
Keyword(s):  
Power Optimization ◽  
Logic Synthesis ◽  
Logic Circuits ◽  
Mixed Polarity

scholarly journals Novel Verification Method for Timing Optimization Based on DPSO

VLSI Design ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-8
Author(s):  
Chuandong Chen ◽  
Rongshan Wei ◽  
Shaohao Wang ◽  
Wei Hu
Keyword(s):  
Logic Synthesis ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Discrete Particle Swarm Optimization ◽  
Timing Optimization ◽  
Verification Method ◽  
Dc Algorithm ◽  
Mixed Polarity ◽  
Critical Paths ◽  
Key Steps

Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

scholarly journals Verification Method for Area Optimization of Mixed-Polarity Reed-Muller Logic Circuits

2018 ◽  
Vol 11 (1) ◽  
pp. 28-34 ◽  
Author(s):  
Chuandong Chen ◽  
◽  
Bing Lin ◽  
Michelle Zhu ◽  
◽  
...  
Keyword(s):  
Logic Circuits ◽  
Verification Method ◽  
Mixed Polarity ◽  
Area Optimization

Power optimization of multi-level logic circuits utilizing circuit symmetries

2000 ◽  
Vol 87 (7) ◽  
pp. 853-864
Author(s):  
Ki-Seok Chung ◽  
Taewhan Kim ◽  
C. L. Liu
Keyword(s):  
Power Optimization ◽  
Logic Circuits ◽  
Multi Level

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies

2020 ◽  
Vol 39 (2) ◽  
pp. 397-410
Author(s):  
Valerio Tenace ◽  
Andrea Calimera ◽  
Enrico Macii ◽  
Massimo Poncino
Keyword(s):  
Logic Synthesis ◽  
Logic Circuits
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