Reader Be Cautious: A Review of "Bias in Mental Testing"Bias in Mental Testing. Arthur R. Jensen

1981 ◽  
Vol 89 (3) ◽  
pp. 305-329 ◽  
Author(s):  
Hill Goldsmith ◽  
John L. Horn
Keyword(s):  
1992 ◽  
Vol 47 (2) ◽  
pp. 244-253 ◽  
Author(s):  
Richard T. von Mayrhauser
Keyword(s):  

1982 ◽  
Vol 37 (1) ◽  
pp. 97-98 ◽  
Author(s):  
Leon J. Kamin
Keyword(s):  

1988 ◽  
Vol 33 (6) ◽  
pp. 485-486
Author(s):  
John B. Carroll
Keyword(s):  

1950 ◽  
Vol 14 (2) ◽  
pp. 159-159
Author(s):  
No authorship indicated
Keyword(s):  

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.


Author(s):  
Paul Lawrie

Throughout U.S. history, the production of difference, whether along racial or disability lines, has been inextricably tied to the imperatives of labor economy. From the plantations of the antebellum era through the assembly lines and trenches of early-twentieth-century America, ideologies of race and disability have delineated which peoples could do which kinds of work. The ideologies and identities of race, work, and the “fit” ’ or “unfit” body informed Progressive Era labor economies. Here the processes of racializing or disabling certain bodies are charted from turn-of-the-century actuarial science, which monetized blacks as a degenerate, dying race, through the standardized physical and mental testing and rehabilitation methods developed by the U.S. army during World War I. Efforts to quantify, poke, prod, or mend black bodies reshaped contemporary understandings of labor, race, the state, and the working body.


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