scholarly journals Moving bumps in theta neuron networks

2020 ◽  
Vol 30 (4) ◽  
pp. 043117 ◽  
Author(s):  
Carlo R. Laing ◽  
Oleh Omel’chenko
Keyword(s):  
2008 ◽  
Vol 0 (0) ◽  
pp. 080804143617793-37
Author(s):  
Sam McKennoch ◽  
Thomas Voegtlin ◽  
Linda Bushnell

2009 ◽  
Vol 21 (1) ◽  
pp. 9-45 ◽  
Author(s):  
Sam McKennoch ◽  
Thomas Voegtlin ◽  
Linda Bushnell

The main contribution of this letter is the derivation of a steepest gradient descent learning rule for a multilayer network of theta neurons, a one-dimensional nonlinear neuron model. Central to our model is the assumption that the intrinsic neuron dynamics are sufficient to achieve consistent time coding, with no need to involve the precise shape of postsynaptic currents; this assumption departs from other related models such as SpikeProp and Tempotron learning. Our results clearly show that it is possible to perform complex computations by applying supervised learning techniques to the spike times and time response properties of nonlinear integrate and fire neurons. Networks trained with our multilayer training rule are shown to have similar generalization abilities for spike latency pattern classification as Tempotron learning. The rule is also able to train networks to perform complex regression tasks that neither SpikeProp or Tempotron learning appears to be capable of.


2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Samir Kumar Bhowmik ◽  
Feras M. Al Faqih ◽  
Md. Nazmul Islam

Space time integration plays an important role in analyzing scientific and engineering models. In this paper, we consider an integrodifferential equation that comes from modelingθ˙neuron networks. Here, we investigate various schemes for time discretization of a theta-neuron model. We use collocation and midpoint quadrature formula for space integration and then apply various time integration schemes to get a full discrete system. We present some computational results to demonstrate the schemes.


2006 ◽  
Vol 73 (4) ◽  
Author(s):  
Yubing Gong ◽  
Bo Xu ◽  
Qiang Xu ◽  
Chuanlu Yang ◽  
Tingqi Ren ◽  
...  

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Silvia Battistoni ◽  
Victor Erokhin ◽  
Salvatore Iannotta

We explore and demonstrate the extension of the synapse-mimicking properties of memristive devices to a dysfunctional synapse as it occurs in the Alzheimer’s disease (AD) pathology. The ability of memristive devices to reproduce synapse properties such as LTP, LTD, and STDP has been already widely demonstrated, and moreover, they were used for developing artificial neuron networks (perceptrons) able to simulate the information transmission in a cell network. However, a major progress would be to extend the common sense of neuromorphic device even to the case of dysfunction of natural synapses. Can memristors efficiently simulate them? We provide here evidences of the ability of emulating the dysfunctional synaptic behavior typical of the AD pathology with organic memristive devices considering the effect of the disease not only on a single synapse but also in the case of a neural network, composed by numerous synapses.


2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040007
Author(s):  
Yang Zhao ◽  
Fengyu Qian ◽  
Faquir Jain ◽  
Lei Wang

In-memory computing is an emerging technique to fulfill the fast growing demand for high-performance data processing. This technique provides fast processing and high throughput by accessing data stored in the memory array rather than dealing with complicated operation and data movement on hard drive. For data processing, the most important computation is dot product, which is also the core computation for applications such as deep learning neuron networks, machine learning, etc. As multiplication is the key function in dot product, it is critical to improve its performance and achieve faster memory processing. In this paper, we present a design with the ability to perform in-memory multi-bit multiplications. The proposed design is implemented by using quantum-dot transistors, which enable multi-bit computations in the memory cell. Experimental results demonstrate that the proposed design provides reliable in-memory multi-bit multiplications with high density and high energy efficiency. Statistical analysis is performed using Monte Carlo simulations to investigate the process variations and error effects.


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