A generic, configurable and efficient architecture for first and second generation discrete wavelet packet transform with ultra-high speed and low-cost FPGA implementation
2018 ◽
Vol 3
(5)
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pp. 116-107
2017 ◽
Vol 2
(3)
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pp. 1129-1136
2010 ◽
Vol 08
(02)
◽
pp. 271-292
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2020 ◽
Vol 11
(03)
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pp. 35-57
1998 ◽
Vol 454
(1976)
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pp. 2243-2266
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2019 ◽
Vol 78
(21)
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pp. 30503-30522
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2019 ◽
Vol 18
(2)
◽