A Boolean OR gate implemented with an optoelectronic switching memristor

2019 ◽  
Vol 115 (15) ◽  
pp. 153504 ◽  
Author(s):  
Jianhui Zhao ◽  
Zhenyu Zhou ◽  
Hong Wang ◽  
Jingjuan Wang ◽  
Weichang Hao ◽  
...  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.


Author(s):  
Martin H. Weik
Keyword(s):  

Optik ◽  
2021 ◽  
pp. 168049
Author(s):  
K R Vijesh ◽  
Titu Thomas ◽  
Manu Vaishakh ◽  
VPN Nampoori ◽  
Sheenu Thomas

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