scholarly journals Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

AIP Advances ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 055001 ◽  
Author(s):  
Kimihiko Kato ◽  
Hiroaki Matsui ◽  
Hitoshi Tabata ◽  
Mitsuru Takenaka ◽  
Shinichi Takagi
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Simulation Analysis ◽  
Group Iv ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Group Iv Semiconductor ◽  
Effect Transistor

scholarly journals Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 227 ◽  
Author(s):  
Young Kim ◽  
Jin Lee ◽  
Geon Kim ◽  
Taesik Park ◽  
HuiJung Kim ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Simulation Analysis ◽  
Field Effect Transistors ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Doping Profile ◽  
Effect Transistor ◽  
Current Characteristics ◽  
Partial Isolation

In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlapped region of the drain and gate, because it causes a high gate-fringing field. Therefore, we suggest guidelines with respect to the optimal PiFET structure.

Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction

2017 ◽  
Vol 139 (2) ◽  
Author(s):  
Valeriy Sukharev ◽  
Jun-Ho Choy ◽  
Armen Kteyan ◽  
Henrik Hovsepyan ◽  
Mark Nakamoto ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Multiscale Simulation ◽  
Oxide Semiconductor ◽  
Compact Modeling ◽  
Electrical Characteristics ◽  
Mobility Shift ◽  
Physical Strain ◽  
Element Analysis ◽  
Effect Transistor

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

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