scholarly journals Experimental prototype of a spin-wave majority gate

2017 ◽  
Vol 110 (15) ◽  
pp. 152401 ◽  
Author(s):  
T. Fischer ◽  
M. Kewenig ◽  
D. A. Bozhko ◽  
A. A. Serga ◽  
I. I. Syvorotka ◽  
...  
Keyword(s):  
Spin Wave ◽  
Majority Gate ◽  
Experimental Prototype

scholarly journals Design of a spin-wave majority gate employing mode selection

2014 ◽  
Vol 105 (15) ◽  
pp. 152410 ◽  
Author(s):  
S. Klingler ◽  
P. Pirro ◽  
T. Brächer ◽  
B. Leven ◽  
B. Hillebrands ◽  
...  
Keyword(s):  
Spin Wave ◽  
Mode Selection ◽  
Majority Gate

scholarly journals Fan-out enabled spin wave majority gate

AIP Advances ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 035119 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
Majority Gate

scholarly journals Non-volatile spin wave majority gate at the nanoscale

AIP Advances ◽  
2017 ◽  
Vol 7 (5) ◽  
pp. 056020 ◽  
Author(s):  
O. Zografos ◽  
S. Dutta ◽  
M. Manfrini ◽  
A. Vaysset ◽  
B. Sorée ◽  
...  
Keyword(s):  
Spin Wave ◽  
Majority Gate

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

scholarly journals Reconfigurable submicrometer spin-wave majority gate with electrical transducers

2020 ◽  
Vol 6 (51) ◽  
pp. eabb4042
Author(s):  
Giacomo Talmelli ◽  
Thibaut Devolder ◽  
Nick Träger ◽  
Johannes Förster ◽  
Sebastian Wintz ◽  
...  
Keyword(s):  
Spin Wave ◽  
Majority Gate ◽  
Computing Systems ◽  
Time Resolved ◽  
Spintronic Devices ◽  
Wave Nature ◽  
Scanning Transmission ◽  
Electrical Spin ◽  
Time Resolved Imaging ◽  
Device Operation

Spin waves are excitations in ferromagnetic media that have been proposed as information carriers in hybrid spintronic devices with much lower operation power than conventional charge-based electronics. Their wave nature can be exploited in majority gates by using interference for computation. However, a scalable spin-wave majority gate that can be cointegrated alongside conventional electronics is still lacking. Here, we demonstrate a submicrometer inline spin-wave majority gate with fan-out. Time-resolved imaging of the magnetization dynamics by scanning transmission x-ray microscopy illustrates the device operation. All-electrical spin-wave spectroscopy further demonstrates majority gates with submicrometer dimensions, reconfigurable input and output ports, and frequency-division multiplexing. Challenges for hybrid spintronic computing systems based on spin-wave majority gates are discussed.

scholarly journals Fanout of 2 Triangle Shape Spin Wave Logic Gates

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gates ◽  
The Other ◽  
Energy Reduction ◽  
Phase Detection ◽  
Majority Gate ◽  
Xor Gate ◽  
Micromagnetic Simulations ◽  
Threshold Detection

Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demonstrate that the proposed structures provide energy reduction of 25%-50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction between 43x and 0.8x when compared to the 16nm and 7nm CMOS while having delay overhead between 11x and 40x.

scholarly journals Fanout of 2 Triangle Shape Spin Wave Logic Gates

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gates ◽  
The Other ◽  
Energy Reduction ◽  
Phase Detection ◽  
Majority Gate ◽  
Xor Gate ◽  
Micromagnetic Simulations ◽  
Threshold Detection

Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demonstrate that the proposed structures provide energy reduction of 25%-50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction between 43x and 0.8x when compared to the 16nm and 7nm CMOS while having delay overhead between 11x and 40x.

scholarly journals Fanout of 2 Triangle Shape Spin Wave Logic Gates

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gates ◽  
The Other ◽  
Energy Reduction ◽  
Phase Detection ◽  
Majority Gate ◽  
Xor Gate ◽  
Micromagnetic Simulations ◽  
Threshold Detection

Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demonstrate that the proposed structures provide energy reduction of 25%-50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction between 43x and 0.8x when compared to the 16nm and 7nm CMOS while having delay overhead between 11x and 40x.

scholarly journals n-bit Data Parallel Spin Wave Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Parallel Processing ◽  
Spin Wave ◽  
Potential Benefit ◽  
Input Data ◽  
Logic Gate ◽  
Object Oriented ◽  
Data Sets ◽  
Majority Gate ◽  
Data Parallel

Due to their very nature, Spin Waves (SWs) created in the same waveguide, but with different frequencies, can coexist while selectively interacting with their own species only. The absence of inter-frequency interferences isolates input data sets encoded in SWs with different frequencies and creates the premises for simultaneous data parallel SW based processing without hardware replication or delay overhead. In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate. Subsequently, to demonstrate the proposed concept, we present 8-bit parallel 3-input Majority gate implementation and validate it by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation. Our evaluation indicates that 8-bit data 3-input Majority gate implementation requires 4.16x less area than the scalar SW gate based equivalent counterpart while preserving the same delay and energy consumption figures.

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