GaAs buffer layer technique for vertical nanowire growth on Si substrate

2014 ◽  
Vol 104 (8) ◽  
pp. 083113 ◽  
Author(s):  
Xiaoqing Xu ◽  
Yang Li ◽  
Kokab B. Parizi ◽  
Yijie Huo ◽  
Yangsen Kang ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Nanowire Growth ◽  
Si Substrate ◽  
Layer Technique ◽  
Gaas Buffer Layer

A Tem Study of Defect Structure in GaAs Film on Si Substrate

1993 ◽  
Vol 325 ◽  
Author(s):  
Sahn Nahm ◽  
Hee-Tae Lee ◽  
Sang-Gi Kim ◽  
Kyoung-Ik Cho
Keyword(s):  
Buffer Layer ◽  
Defect Structure ◽  
Stacking Faults ◽  
Misfit Dislocations ◽  
Gaas Film ◽  
Si Substrate ◽  
Moiré Fringes ◽  
Gaas Films ◽  
Layer Stacking ◽  
Gaas Buffer Layer

AbstractFor the GaAs buffer layer deposited on Si substrate at 80°C and annealed at 300°C for 10 min, the size of most GaAs islands was observed as ∼ 10 nm but large islands (∼ 40 nm) were also seen. According to the calculation of spacing of moire fringes, large GaAs islands are considered to be rotated about 4 ° with respect to the Si substrate normal. However, for the main GaAs film overgrown on the GaAs buffer layer at 580 °C, moire fringes with the spacing of 5 nm (GaAs film without rotation) completely covered the surface of Si substrate. Misfit dislocations and stacking faults were already formed at the growth stage of buffer layer. Stacking faults and misfit dislocations consisting of Lomer and 60 ° dislocations were observed in GaAs films grown at 580 °C. However, after rapid thermal annealing at 900 °C for 10 sec, only Lomer dislocations with 1/2[110] and 1/2[-110] Burgers vectors were observed.

Material Properties of GaAs-on-Si and Fabrication of Digital Integrated Circuits

1988 ◽  
Vol 116 ◽  
Author(s):  
N. Clhand ◽  
F. Ren ◽  
S. N. G. Chu ◽  
A. M. Sergent ◽  
T. Boone ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Buffer Layer ◽  
Cross Sections ◽  
Power Dissipation ◽  
Propagation Delay ◽  
Si Substrate ◽  
Digital Integrated Circuits ◽  
Lower Growth ◽  
Gaas On Si ◽  
Gaas Buffer Layer

AbstractWe have found that the surface morphology of GaAs grown on Si by MBE is smoother at lower growth temperatures (<500° C), but that the crystalline properties improve at higher growth temperatures (575-600°C). After thermal annealing at 850°C for 15 rai the TEM plan-views indicate that the dislocation density on the surface is reduced by a factor of 4 only. However, the TEM cross-sections indicate a much larger reduction of dislocations in highly dislocated regions near the GaAs/Si interface. Dislocations which are loops or tangles tend to shrink and clean up after annealing leaving a larger volume of GaAs free from, or with fewer, dislocations. The density of electron deep levels reduces with increasing thickness. Electron traps M1, M3 and M4 are not seen when a high purity As is used. For high device performance, the GaAs buffer layer thickness should be at least 2 µm. Although the wafer warpage increases from 7 µm to 52 µm as the GaAs thickness increases from 1.2 µm to 4.2 µm on 7.5 cm wafers, the wafers are as fiat as the original Si wafers under vacuum clamping. Wafer warpage reduced significantly when GaAs was grown selectively through a Si shadow mask. For 1 µm gate MESFET's, σvT was 65 mV on a 3.5 × 3 cm2 wafer area with gmax = 153 mS/ram. A minimum propagation delay of 52 ps/stage at a power dissipation of 1.3 mW/gate was measured for the 19 stage DCFL ring oscillators with 40= yield. Conductivity of the Si substrate and GaAs buffer layer posed no problem in channel isolation. The divide-by-two circuits performed the frequency dividing operation up to 1.8 GHz. The study shows that GaAs-on-Si has a great potential for digital IC's.

Beam Induced Lateral Epitaxy of GaAs on a GaAs/Si Template

2004 ◽  
Vol 829 ◽  
Author(s):  
Shigeya Naritsuka ◽  
Koji Saitoh ◽  
Toshiyuki Kondo ◽  
Takahiro Maruyama
Keyword(s):  
Buffer Layer ◽  
Stacking Faults ◽  
Heteroepitaxial Growth ◽  
Si Substrate ◽  
Growth Region ◽  
Gaas Buffer Layer ◽  
Device Applications ◽  
Lateral Epitaxy

ABSTRACTBeam induced lateral epitaxy (BILE) on truncated ridges was applied to the heteroepitaxial growth of GaAs on a Si substrate. A GaAs buffer layer was formed on the Si substrate, and then this GaAs/Si template was used as a substrate for the BILE process. As a result, overgrown regions of GaAs of widths as large as 6.5 μm were grown laterally from the sides of the truncated ridges. The growth regions had a flat, smooth top surface consisting of a (111) facet. Although stacking faults from the GaAs/Si template remained in the growth region, which are unfavorable for device applications, the lateral grown region has no dislocations. Thus, the BILE method is useful for reducing dislocations in heteroepitaxy.

Heteroepitaxial Growth of 3C-SiC on Si (111) Substrate Using AlN as a Buffer Layer

2008 ◽  
Vol 600-603 ◽  
pp. 251-254 ◽  
Author(s):  
Yong Mei Zhao ◽  
Guo Sheng Sun ◽  
Xing Fang Liu ◽  
Jia Ye Li ◽  
Wan Shun Zhao ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Chemical Vapor ◽  
Heteroepitaxial Growth ◽  
Si Substrate ◽  
Si Substrates ◽  
Good Crystallinity ◽  
Aln Film ◽  
Pressure Chemical ◽  
Aln Buffer ◽  
Sic Film

Using AlN as a buffer layer, 3C-SiC film has been grown on Si substrate by low pressure chemical vapor deposition (LPCVD). Firstly growth of AlN thin films on Si substrates under varied V/III ratios at 1100oC was investigated and the (002) preferred orientational growth with good crystallinity was obtained at the V/III ratio of 10000. Annealing at 1300oC indicated the surface morphology and crystallinity stability of AlN film. Secondly the 3C-SiC film was grown on Si substrate with AlN buffer layer. Compared to that without AlN buffer layer, the crystal quality of the 3C-SiC film was improved on the AlN/Si substrate, characterized by X-ray diffraction (XRD) and Raman measurements.

Characterization of GaAs buffer layer function in GaAs/InP strained structure grown by MBE

1996 ◽  
Vol 286 (1-2) ◽  
pp. 107-110 ◽  
Author(s):  
Ching-Ting Lee ◽  
Chi-Yu Wang ◽  
Yeong-Chang Chou
Keyword(s):  
Buffer Layer ◽  
Layer Function ◽  
Gaas Buffer Layer

Ferroelectric and piezoelectric properties of highly oriented Pb(Zr,Ti)O3 film grown on Pt/Ti/SiO2/Si substrate using conductive lanthanum nickel nitrate buffer layer

2005 ◽  
Vol 20 (3) ◽  
pp. 726-733 ◽  
Author(s):  
Jong-Jin Choi ◽  
Gun-Tae Park ◽  
Chee-Sung Park ◽  
Hyoun-Ee Kim
Keyword(s):  
Thin Film ◽  
Buffer Layer ◽  
Lead Zirconate Titanate ◽  
Piezoelectric Properties ◽  
Nickel Nitrate ◽  
Si Substrate ◽  
Pzt Thin Film ◽  
Pzt Films ◽  
Lanthanum Nickel ◽  
Ferroelectric And Piezoelectric Properties

The orientation and electrical properties of Pb(Zr,Ti)O3 thin films deposited on a Pt/Ti/SiO2/Si substrate using lanthanum nickel nitrate as a conductive buffer layer were analyzed. The lanthanum nickel nitrate buffer layer was not only electrically conductive but also effective in controlling the texture of the lead zirconate titanate (PZT) thin film. The role of the lanthanum nickel nitrate buffer layer and its effects on the orientation of the PZT thin film were analyzed by x-ray diffraction, electron beam back-scattered diffraction, and scanning electron microscopy. The annealed lanthanum nickel nitrate buffer layer was sufficiently conducting for use in longitudinal electrode configuration devices. The dielectric, ferroelectric, and piezoelectric properties of the highly (100) oriented PZT films grown with the lanthanum nickel nitrate buffer layer were measured and compared with those of (111) and (100) oriented PZT films deposited without a buffer layer.

The study of temperature dependent strain in Ge epilayer with SiGe/Ge buffer layer on Si substrate with different thickness

2014 ◽  
Vol 104 (24) ◽  
pp. 241605 ◽  
Author(s):  
Po-Hung Wu ◽  
Ying-Sheng Huang ◽  
Hung-Pin Hsu ◽  
Cheng Li ◽  
Shi-Hao Huang ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Si Substrate ◽  
Temperature Dependent ◽  
Dependent Strain ◽  
Different Thickness

scholarly journals Liquid phase epitaxial growth of high quality GaAs on InP using Se‐doped GaAs buffer layer and grating‐patterned substrates

1995 ◽  
Vol 66 (19) ◽  
pp. 2531-2533 ◽  
Author(s):  
Dong‐Keun Kim ◽  
Ju‐Heon Ahn ◽  
Byung‐Teak Lee ◽  
H. J. Lee ◽  
S. S. Cha ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Epitaxial Growth ◽  
Buffer Layer ◽  
Patterned Substrates ◽  
High Quality ◽  
Liquid Phase Epitaxial ◽  
Gaas Buffer Layer ◽  
Liquid Phase Epitaxial Growth

An Application of the Buffer Layer Technique to Computations of Flow in Turbomachinery

2004 ◽  
pp. 299-309 ◽  
Author(s):  
Franco Magagnato ◽  
Jaroslaw Rachwalski ◽  
Martin Gabi
Keyword(s):  
Buffer Layer ◽  
Layer Technique
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